Power management adapted to compute average length of time that a processor is idle during each processing cycle from synchronization signals

A SIMD processor architecture for processing a stream of data vectors, the architecture comprising:

• a processor array comprising a plurality of processors, each processor being adapted to process a data element in each vector, the operation of the processor array being controlled by a local clock signal having a first frequency;
• a control processor adapted to control the operation of the SIMD processor architecture and generate synchronisation signals to synchronise the operation of the processor array with the stream of data vectors, the operation of the control processor being controlled by a local clock signal having a second frequency;
• and
• power management means for adjusting the frequencies of the local clock signals in response to the synchronisation signals generated by the control processor, thereby minimising the power consumption of the SIMD processor architecture, wherein the rare at which data vectors arrive at the SIMD processor architecture varies over time, the frequencies of the clock signals are adjusted to reduce the time that the processor array is idle, and the power management means is adapted to compute the average length of time that the processor array is idle during each processing cycle from the synchronisation signals.