Method and apparatus for providing for detecting processor state transitions
AssigneeIntel Corporation
InventorsVasudevan Srinivasan, Susumu Arai, Barnes Cooper
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Abstract
In some embodiments, the method and apparatus to provide for the detection of processor transition states is described. Some embodiments include at least two threads which provide detection for high and low priority states, which provide for power state transitions by the operating system: The low priority thread runs just prior to entry into an idle or low power state; the high priority thread runs when the idle state is ended or the highest power state is reached. In some embodiments, the use of these threads provides for the detection of processor state transitions and idle times independently of the operating system. Other embodiments are described.
Claims24
A method, comprising:
- creating a high priority thread to be executed by a processor at substantially a highest priority among other threads;
- creating a low priority thread to be executed by a processor at substantially a lowest priority among other threads;
- creating a shared memory, wherein the shared memory is accessible by the high priority thread and the low priority thread;
- and
- detecting power management state transitions for a processor using the high priority thread that is executed by the processor when an idle state is ended or a high power state is reached and the low priority thread that is executed by the processor prior to entry into an idle or low power state.
An article comprising a computer-readable storage medium containing instructions that if executed by a processor enable a system to:
- creating a high priority thread to be executed by a processor at substantially a highest priority among other threads;
- creating a low priority thread to be executed by a processor at substantially a lowest priority among other threads;
- creating a shared memory, wherein the shared memory is accessible by the high priority thread and the low priority thread;
- and
- detecting power management state transitions for a processor using the high priority thread that is executed by the processor when an idle state is ended or a high power state is reached and the low priority thread that is executed by the processor prior to entry into an idle or low power state.
An apparatus, comprising:
- a machine accessible medium, and
- instructions encoded in the machine accessible medium, wherein the instructions, when executed in a computing system, cause the computing system to perform operations comprising:
- creating a high priority thread to be executed by a processor at substantially a highest priority among other threads;
- creating a low priority thread to be executed by a processor at substantially a lowest priority among other threads;
- creating a shared memory, wherein the shared memory is accessible by the high priority thread and the low priority thread;
- and
- detecting power management state transitions for a processor using the high priority thread that is executed by the processor when an idle state is ended or a high power state is reached and the low priority thread that is executed by the processor prior to entry into an idle or low power state.
A computing system, comprising:
- a machine accessible medium;
- a processor responsive to the machine accessible medium;
- and
- instructions encoded in the machine accessible medium, wherein the instructions, when executed by the processor, perform operations comprising:
- creating a high priority thread to be executed by a processor at substantially a highest priority among other threads;
- creating a low priority thread to be executed by a processor at substantially a lowest priority among other threads;
- creating a shared memory, wherein the shared memory is accessible by the high priority thread and the low priority thread;
- and
- detecting power management state transitions for a processor using the high priority thread that is executed by the processor when an idle state is ended or a high power state is reached and the low priority thread that is executed by the processor prior to entry into an idle or low power state.
Dependencies are inferred from the claim text.