Debug instruction for use in a data processing system

A data processing system, comprising:

• instruction fetch circuitry for receiving debug instructions, the debug instructions comprising a first debug instruction and a second debug instruction, the second debug instruction comprising a field to indicate a group number;
• a plurality of debug control register fields, wherein a first one of the plurality of debug control register fields is associated with the first debug instruction and wherein the group number associates a second one of the plurality of debug control register fields to the second debug instruction;
• and
• debug execution control circuitry, coupled to the instruction fetch circuitry and to the debug control register field, the debug execution control circuitry controlling execution of the first debug instruction in a first manner if the first one of the debug control register fields has a first value, and the debug execution control circuitry controlling execution of the first debug instruction in a second manner if the first one of the debug control register fields has a second value, wherein in the first manner a debug operation is performed, and wherein in the second manner no debug operation is performed, and the debug execution control circuitry controlling execution of the second debug instruction in a third manner if the second one of the debug control register fields has a third value and in a fourth manner if the second one of the debug control register fields has a fourth value, wherein in the third manner a debug operation is performed, and wherein in the fourth manner no debug operation is performed.