Method and system for restoring register mapper states for an out-of-order microprocessor

A processor comprising:

• an instruction sequencing unit (ISU) that fetches instructions;
• an execution unit that executes instructions, wherein at least some of said instructions are executed speculatively;
• a map table data structure that maps a logical register to a physical register in response to a first instruction;
• means for recording a second instruction as a most recently dispatched instruction in said map table data structure when said second instruction maps said logical register to said physical register;
• means for setting an evictor instruction tag (ITAG) of said first instruction in said map table data structure when said second instruction maps to a same logical register of said first instruction;
• means for detecting a mispredicted speculative instruction;
• means for determining which instructions in said map table data structure were dispatched prior to said mispredicted speculative instruction;
• and
• means for restoring said map table data structure to a state prior to said mispredicted speculative instruction by utilizing said evictor ITAG to restore one or more A bits in said map table data structure.

A computer-readable medium encoded with a computer program that, when executed, performs the steps of:

• mapping a logical register to a physical register in a map table data structure in response to a first instruction;
• recording a second instruction as a most recently dispatched instruction in said map table data structure when said second instruction maps said logical register to said physical register, wherein said second instruction is executed speculatively by an execution unit;
• setting an evictor instruction tag (ITAG) of said first instruction in said map table data structure when said second instruction maps to a same logical register of said first instruction;
• detecting a mispredicted speculative instruction;
• determining which instructions in said map table data structure were dispatched prior to said mispredicted speculative instruction;
• and
• restoring said map table data structure to a state prior to said mispredicted speculative instruction by utilizing said evictor ITAG to restore one or more A bits in said map table data structure.