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AssigneeInternational Business Machines Corporation
InventorsHarm Peter Hofstee, Charles Ray Johns, James Allan Kahle
Estimating the term…
A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
A method for sharing a memory between a plurality of heterogeneous processors, said method comprising:
Dependencies are inferred from the claim text.
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User address space allocation, e.g. contiguous or non contiguous base addressing: multiple user address space allocation, e.g. using different…
Based on arbitration: in a multiprocessor architecture
Computing and data processing
Term ended 21 Nov 2024 (estimated)
1. Technical Field
The present invention relates in general to a system for sharing memory by heterogeneous processors. More particularly, the present invention relates to a system for sharing memory by heterogeneous processors that are included in an integrated circuit whereby each heterogeneous processor is adapted to process its own instruction set.
2. Description of the Related Art
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items.
FIG. 1 illustrates the overall architecture of a computer network in accordance with the present invention;
FIG. 2 is a diagram illustrating the structure of a processing unit (PU) in accordance with the present invention;
The following is intended to provide a detailed description of an example of the invention and should not be taken to be limiting of the invention itself. Rather, any number of variations may fall within the scope of the invention which is defined in the claims following the description.
The overall architecture for a computer system 101 in accordance with the present invention is shown in FIG. 1. As illustrated in this figure, system 101 includes network 104 to which is connected a plurality of computers and computing devices. Network 104 can be a LAN, a global network, such as the Internet, or any other computer network.
The computers and computing devices connected to network 104 (the network's “members”) include, e.g., client computers 106, server computers 108, personal digital assistants (PDAs) 110, digital television (DTV) 112 and other wired or wireless computers and computing devices. The processors employed by the members of network 104 are constructed from the same common computing module. These processors also preferably all have the same ISA and perform processing in accordance with the same instruction set. The number of modules included within any particular processor depends upon the processing power required by that processor.