US 7,689,782 B1Granted

Processor instruction used to determine whether to perform a memory-related trap

AssigneeAzul Systems, Inc.

InventorsJack Choquette, Gil Tene, Michael A. Wolf

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Abstract

An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.

Claims30

Dependent claims

A method comprising:

fetching an instruction that comprises:
a first set of one or more bits identifying the instruction;
and
a second set of one or more bits associated with a first address value;
executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test;
wherein:
the second set of one or more bits is used in the determination of whether to perform the trap;
the determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access;
the selection of the at least one test is based at least in part on a configuration option;
and
the plurality of tests includes:
a marking test based at least in part on a group of one or more marker bits included in the first address value;
and
a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein:
the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits;
and
the plurality of managed memory types include garbage collection generation, heap, and stack.

14 more elements

A computer system comprising:

a processor configured to:
fetch an instruction;
and
execute the instruction to determine whether to perform a trap operation, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and performing the at least one test;
and
a memory coupled with the processor, wherein the memory is configured to provide the processor with the instruction, wherein the instruction includes:
a first set of one or more bits identifying the instruction;
and
a second set of one or more bits associated with a first address value;
wherein:
the second set of one or more bits is used in the determination of whether to perform the trap;
the determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access;
the selection of the at least one test is based at least in part on a configuration option;
and
the plurality of tests includes:
a marking test in which a group of one or more marker bits included in the first address value is used to determine whether to perform a trap;
and
a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one type of managed memory to another type of managed memory and generates a trap in the event that the data value is determined to be escaping from one type of managed memory to another type of managed memory, wherein:
the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits;
and
the managed memory types include garbage collection generation, heap, and stack.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/296,195Filed 6 Dec 2005 · continuation in part
Priority: 4 Aug 2003
Granted: 30 Mar 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 12/0253
Free address space management: garbage collection, i.e. reclamation of unreferenced memory
G06F 9/30003
Arrangements for executing machine instructions, e.g. instruction decode: arrangements for executing specific machine instructions
G06F
Computing and data processing

Family

Application60/492,585Us provisional application · filed 4 Aug 2003
Application10/701,388Parent of this continuation-in-part · filed 4 Nov 2003
Application11/031,015Parent of this continuation-in-part · filed 7 Jan 2005
US 7,117,318 B1Parent of this continuation-in-part
US 7,469,324 B2Parent of this continuation-in-part
US 2006/0155791 A1Published application
US 7,689,782 B1This patent

From the US filing history. Foreign family members aren’t listed.