Methods and apparatus for estimating fair cache miss rates on a chip multiprocessor
AssigneeSun Microsystems, Inc.
InventorAlexandra Fedorova
Life of this patent
Estimating the term…
Abstract
A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently. Additionally, the caching estimator process computes the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads. As a result, the caching estimator applies the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.
Claims20
A method for estimating the fair cache miss rate of a thread executing on a chip multiprocessor having a plurality of processing cores, the method comprising:
- identifying a thread for determining the fair cache miss rate of the thread;
- executing the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently;
- computing the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads;
- and
- applying the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.
A computerized device comprising:
- a memory;
- a chip multiprocessor;
- a communications interface;
- an interconnection mechanism coupling the memory, the chip multiprocessor and the communications interface;
- and
- wherein the memory is encoded with a caching estimator application that when executed on the chip multiprocessor provides a caching estimator process causing the computerized device to be capable of performing the operations of:
- identifying a thread for determining the fair cache miss rate of the thread;
- executing the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently;
- computing the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads;
- and
- applying the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.
A computer program product having a computer readable medium operable to store computer program logic embodied in computer program code encoded thereon as an encoded set of chip multiprocessor based instructions for performing cache miss rate estimation comprising:
- computer program code for identifying a thread for determining the fair cache miss rate of the thread;
- computer program code for executing the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently;
- computer program code for computing the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads;
- computer program code for estimating a linear relationship between the actual cache miss rate of the thread and the actual cache miss rates of the plurality of peer threads, wherein estimating the linear relationship provides linear parameters for a gradient value and a constant value;
- and
- computer program code for applying the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.
A computerized device comprising:
- a memory;
- a chip multiprocessor;
- a communications interface;
- an interconnection mechanism coupling the memory, the chip multiprocessor and the communications interface;
- and
- wherein the memory is encoded with caching estimator application that when executed on the chip multiprocessor provides a means for estimating cache miss rates on the chip multiprocessor comprising:
- means for identifying a thread for determining the fair cache miss rate of the thread;
- means for executing the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently;
- means for computing the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads;
- means for estimating a linear relationship between the actual cache miss rate of the thread and the actual cache miss rates of the plurality of peer threads, wherein estimating the linear relationship provides linear parameters for a gradient value and a constant value;
- and
- means for applying the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.
Dependencies are inferred from the claim text.