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US 7,689,772 B2Granted
Power-performance modulation in caches using a smart least recently used scheme
AssigneeIntel Corporation
InventorsSatish Damaraju, Subramaniam Maiyuran, Truyen Trinh, Parag Raval, Peter Smith
Life of this patent
Estimating the term…
Abstract
The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.
Claims24
An apparatus comprising:
- an N-way set associative sequential cache;
- and
- a way selector coupled to the N-way set associative sequential cache, the way selector to direct access for a range of addresses to a subset of N-ways in the N-way set associative sequential cache, the subset of N-ways allocated to the range of addresses;
- wherein a portion of high order bits of a linear an instruction pointer is used to select the subset of N-ways, the portion of high order bits selected based on the sequential order of the cache.
1 more element
A method comprising:
- providing an N-way set associative sequential cache;
- and
- directing access for a range of addresses to a subset of N-ways in the N-way set associative sequential cache, the subset of N-ways allocated to the range of addresses;
- wherein high order bits of a linear a instruction pointer is used to select the subset of N-ways, the portion of high order bits selected based on the sequential order of the cache.
1 more element
An article including a computer readable storage medium having associated information, wherein the information, when accessed, results in a machine performing:
- providing an N-way set associative sequential cache;
- and
- directing access for a range of addresses to a subset of N-ways in the N-way set associative sequential cache, the subset of N-ways allocated to the range of addresses;
- wherein high order bits of a linear instruction pointer is used to select the subset of N-ways, the portion of high order bits selected based on the sequential order of the cache.
1 more element
A system comprising:
- a Dynamic Random Access memory;
- and
- a processor coupled to the Dynamic Random Access memory, the processor comprising:
- an N-way set associative sequential cache;
- and
- a way selector coupled to the N-way set associative sequential cache, the way selector to direct access for a range of addresses to a subset of N-ways in the N-way set associative sequential cache, the subset of N-ways allocated to the range of addresses;
- wherein a portion of high order bits of a linear instruction pointer is used to select the subset of N-ways, the portion of high order bits selected based on the sequential order of the cache.
4 more elements
Dependencies are inferred from the claim text.