Coherency management of castouts
AssigneeInternational Business Machines Corporation
InventorsJames S. Fields, Jr., Guy L. Guthrie, William J. Starke, Derek E. Williams
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Abstract
According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
Claims10
A method of coherency management in a multi-processor data processing system having multiple upper level cache memories and a lower level cache memory, said method comprising:
- removing a cache line from a first of the multiple upper level cache memories and transmitting a castout request for the cache line from the first upper level cache memory to a lower level cache memory, said castout request including an indication of an exclusive ownership coherency state;
- in response to the castout request, placing the cache line in the lower level cache memory in said exclusive ownership coherency state and recording a source indication at said lower level cache indicating which of said multiple upper level cache memories was a source of said cache line;
- and
- in response to a subsequent data request from one of the multiple upper level cache memories, the lower level cache memory determining by reference to said source indication whether the data request was received from the source of the cache line, and if so, supplying the cache line in response to the data request in the exclusive ownership coherency state.
A data processing system, comprising:
- first and second processor cores;
- and
- a first upper level cache memory coupled to the first processor core and a second upper level cache memory coupled to the second processor core;
- a lower level cache memory coupled to the first upper level cache memory and to the second upper level cache memory, said lower level cache memory including:
- a data array;
- a directory of contents of said data array;
- a cache controller that, responsive to receipt of a castout request indicating an exclusive ownership state, places the cache line in the data away in said exclusive ownership coherency state and records a source indication in said directory indicating which of said multiple upper level cache memories was a source of said cache line, wherein said cache controller, responsive to a subsequent data request from one of the multiple upper level cache memories, determines by reference to said source indication whether the data request was received from the source of the cache line, and if so, supplies the cache line in response to the data request in the exclusive ownership coherency state.
Dependencies are inferred from the claim text.