Method and system for selectively permitting cache memory access during a cache miss request

A cache memory control circuit that controls a cache memory in the case where a cache miss occurs for a first move-in request that precedes a second move-in request to the cache memory and a move-in buffer is being acquired, the move-in buffer including information concerning an upper address section of a replace address corresponding to a move-in request and information indicating whether a replace destination is a clean victim block that need not to be written back and is valid, the circuit comprising:

• a first determination section that determines, before a tag search, whether a second index and upper address section of a second request address related to the second move-in request do not correspond respectively to a first index and upper address section of a first request address which is related to the preceding first move-in request and which has been registered in the move-in buffer;
• a third determination section that determines whether an index and upper address section in the second address related to the second move-in request and those in the replace address that is related to the preceding first move-in request and has been registered in the move-in buffer do not correspond respectively to each other;
• and
• a second replacing section that replaces the replace destination for the second move-in request in the case where the first determination section determines that the second request address does not correspond to the first request address that has been registered in the move-in buffer, and where the third determination section determines the index and upper address section in the second address related to the second move-in request and those in the replace address that is related to the preceding first move-in request and has been registered in the move-in buffer do not correspond respectively to each other and the replace destination is the clean victim block.

A cache memory control method that controls a cache memory when a cache miss occurs for a first move-in request that precedes a second move-in request to the cache memory and a move-in buffer is being acquired, comprising:

• determining, before a tag search, whether a second index and upper address section of a second request address related to the second move-in request do not correspond respectively to a first index and upper address section of a first request address which is related to the preceding first move-in request and which has been registered in the move-in buffer;
• performing a tag search related to the second move-in request;
• determining whether an index in the second request address related to the second move-in request and a way in the cache hit and an index in the first request address related to the preceding first move-in request and a replace way in the cache that have been registered in the move-in buffer do not correspond respectively to each other in a case where a cache hit has been determined in the tag search;
• continuing replacing for the second move-in request when determined that the second request address does not correspond to the first request address which has been registered in the move-in buffer and the move-in buffer includes information indicating that a replace destination is a clean victim block that need not to have written back and is valid,
• wherein the replacing for the second move-in request is continued when determined as the index in the second request address related to the second move-in request and the way the hit cache and an index in the first request address related to the preceding first move-in request and the replace way in the cache that have been registered in the move-in buffer do not correspond respectively to each other in the determining.

A cache memory control method that controls a cache memory when a cache miss occurs for a first move-in request that precedes a second move-in request to the cache memory and a move-in buffer is being acquired, and the move-in buffer including information concerning an upper address section of a replace address corresponding to a move-in request and information indicating whether a replace destination is a clean victim block that need not to be written back and is valid, the method comprising:

• determining, before a tag search, whether a second index and upper address section of a second request address related to the second move-in request do not correspond respectively to a first index and upper address section of a first request address which is related to the preceding first move-in request and which has been registered in the move-in buffer, as well as determining whether the first index and upper address section in the second address related to the second move-in request and those in the replace address that is related to the preceding first move-in request and has been registered in the move-in buffer do not correspond respectively to each other;
• and
• continuing replacing the replacing the replace destination for the second move-in request when determined that the second request address does not correspond to the first request address that has been registered in the move-in buffer and when determined that the index and upper address section in the second address related to the second move-in request and those in the replace address that is related to the preceding first move-in request and has been registered in the move-in buffer do not correspond respectively to each other and the replace destination is the clean victim block.