Dual bus matrix architecture for micro-controllers

A method comprising:

• receiving requests to access shared memory resources at a shared multiport memory controller of a microcontroller from a plurality of high performance peripherals through a first interconnect matrix of the microcontroller and from a plurality of limited bandwidth peripherals through a second interconnect matrix of the microcontroller;
• and
• routing access to the shared memory resources according to a scheduling algorithm in response to receiving the requests,
• wherein routing access includes routing access of one of the plurality of high performance peripherals to a shared high performance memory resource through the first interconnect matrix when the shared high performance memory resource is not busy, and routing access of one of the plurality of limited bandwidth peripherals to a shared limited bandwidth memory resource through the second interconnect matrix when the shared limited bandwidth memory resource is not busy.