Interrupt control function adapted to control the execution of interrupt requests of differing criticality

#This invention relates to control of the execution of interrupts in a processor, especially a processor in a system designed to support both critical and non-critical processes.

#Most common computing systems, such as personal computers, do not have to deal with severe real-time requirements. Though there are applications, such as media streaming, which do impose significant processing loads on the processor, if the requirements exceed the processing capability of the machine for short periods the result is a minor artefact in the replayed stream (provided that there are adequate error recovery provisions) which the viewer tends to overlook. On the other hand, such systems place a premium on flexibility and frequently use “open operating systems” such as Microsoft Windows or Linux. These systems allow anyone to write software that will run on any computer running the OS, whatever its hardware specification. The result is that there is frequent conflict between different applications; and often the user finds it very hard to make a piece of software work correctly because of differences between the assumed and actual hardware performance and configuration.

#There are also processor applications where the processor needs to meet severe real-time constraints and where the consequences of failure can (sometimes literally) be fatal. Examples are flight control systems for aircraft; engine management systems; and processors used in mobile communications devices. In these applications it is usual to control very carefully the software that is permitted to run in the processor; to test it rigorously; and often to segregate the hardware so that non-critical software runs on other processors.

#The invention will now be described by way of example with reference to the accompanying drawings in which:

#FIG. 1 shows a schematic diagram of a timing critical system incorporating an interrupt control function according to the invention,

#FIG. 2 is a diagram showing an overview of the operations occurring within the timing critical system of FIG. 1,

#FIG. 1 illustrates a computing system comprising a computer platform 4 including a processor 7, a memory 20 and a generic computer operating system 5. A real time, timing critical system 8 runs on the platform 4 together with additional applications 6 which are not timing critical.

#The timing critical system 8 has one or more sources of interrupt requests (IRQs) associated with it, which are designated as critical interrupts 11, and each source is marked as critical by a flag 13 which is set. Each critical interrupt 11 has associated with it an interrupt service routine (ISR) 2, which is executed by the processor 7 when triggered by the critical interrupt 11. The timing critical system 8 also has critical tasks 3 associated with it which are of lower priority than the critical interrupts 11.

#The other applications 6 also have one or more sources of interrupt requests (IRQs) associated with them, which are designated as non-critical interrupts 12 and marked as non-critical by said flag 13 not being set. Each non-critical interrupt 12 has associated with it a non-critical interrupt service routine (ISR) 9 which is executed by the processor 7 when triggered by a non-critical interrupt 12. The other applications also have non-critical tasks 17 associated with them.