US 7,689,748 B2 · Event handler for context-switchable and non-context-switchable processing tasks

Abstract

Embodiments of a system and method for handling interrupts are described herein. In an embodiment interrupts from various client components in a system (also referred to as clients) are processed by an interrupt handler component uniformly. The various clients signal interrupts in different manners. For example, some clients signal interrupts in a level-based manner, and some clients signal interrupts in a pulse-based manner. In an embodiment, all interrupts received by the interrupt handler are formed into an event message according to a uniform format regardless of the manner in which the interrupt is signaled. The event message includes all information necessary for a host processor interrupt service routine (ISR) to service the interrupts without reading hardware registers. Event messages are stored in an event buffer for access and handling by the host. The event buffer is managed by the interrupt handler.

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Claims41

Dependent claims

A system comprising:

a plurality of clients that perform processing tasks, and that signal interrupts in one or more of a plurality of manners;
an interrupt handler coupled via a system bus to a host interface controller, at least one host processor, and through a memory controller to a system memory, the interrupt handler further coupled directly to the plurality of clients, wherein the interrupt handler is operable,
to receive interrupts signaled by the plurality of clients;
to arbitrate among the received interrupts to determine in what order the received interrupts are to be handled;
to form an event message for each received interrupt signaled in one or more of the plurality of manners, wherein forming an event message comprises forming different event messages for different types of clients that;
and
to request the memory controller to write the event messages in an event buffer, such that the event messages are accessible via the system bus to the at least one host processor for processing as interrupts, wherein the at least one host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt.

4 more elements

A system comprising:

a plurality of components that perform tasks and report events, wherein the plurality of components comprises level-based components and pulse based components, and wherein the level-based components perform permanent tasks and the pulse-based components perform volatile tasks, wherein a permanent task involves a single thread of execution, and a volatile task involves multiple threads of execution by allowing its state to be saved and restored at selected points in time;
and
an event handler coupled directly to the plurality of components, and further coupled via a system bus to a host interface controller, at least one host processor, and through a memory controller to a system memory, wherein the event handler is operable,
to receive interrupts signaled by the plurality of components, including different types of interrupts for the level-based components and the pulse based components;
to arbitrate among the received interrupts to determine in what order the received interrupts are to be handled;
to form an event message for each received interrupt signaled, including event messages in a consistent format for the different types of interrupts;
and
to request the memory controller to write the event messages in an event buffer, such that the event messages are accessible via the system bus to the at least one host processor for processing as interrupts, wherein the at least one host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt.

5 more elements

Dependencies are inferred from the claim text.

Description7,109 words

Summary940 words

#The invention is in the field of scheduling operations in complex data processing systems.

#In typical complex data processing systems, many different processing tasks or operations are being performed by multiple sub-units of the system at any one time. Usually, all of the operations of the system are under the control of a host processor, or central processing unit (CPU) that runs a particular operating system (OS). The CPU communicates with various input/output (IO) units of the system through one or more buses, such as a peripheral component interface (PCI) bus or a PCI Express (PCIE) bus for example.

#The host processor manages operations in the system, including execution of various tasks by various IO units. The IO units must necessarily communicate a lot of information with the host processor in a manner dictated by the OS. For example, when a task is executing on an IO unit and becomes stalled or interrupted, perhaps because of lack of particular data for example, the IO unit generates an interrupt to the host processor in such a way that the host processor can identify the IO unit and the cause of the interrupt, “fix” the cause of the interrupt, and signal the IO unit that the problem is fixed and that it can proceed with the task. Traditionally, interrupts are signaled by the IO unit writing a value to an interrupt status register. According to one scheme, an interrupt status register may contain multiple bits, any one of which signals an interrupt when it is a particular value, such as a logic “1” (also referred to as a logic high). The values in the interrupt status register are OR'd and if any of the values is high, an interrupt signal is sent to the host processor, which must perform a register read to determine which bit or bits are high. The host processor also must perform a register write to clear interrupts after fixing their causes. This interrupt scheme is sometimes referred to as level-based, because the level of the interrupt bit and line remains at the level set by the IO unit until the interrupt is cleared by the host processor.

Brief description of the drawings5 figures

#FIG. 1 is a block diagram of a system according to an embodiment.

#FIG. 2 is a block diagram of an interrupt handler according to an embodiment.

#FIG. 3 is a block diagram of an adapter for level-based clients according to an embodiment.

Detailed description6,084 words

#In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 102 is first introduced and discussed with respect to FIG. 1).

#Embodiments of a system and method for handling interrupts are described herein. In an embodiment events, or interrupts from various client components in a system (also referred to as clients) are processed by one event handler, or interrupt handler component uniformly. The various clients signal interrupts in different manners. For example, some clients signal interrupts in a level-based manner, and some clients signal interrupts in a pulse-based manner. In an embodiment, the non-context switchable, level-based components perform permanent tasks, and the pulse based, context switchable components perform serialized volatile tasks. In an embodiment, a permanent task involves a single thread of execution, while a volatile task involves multiple threads of execution by allowing its state to be saved and restored at selected points in time.

#In an embodiment, each interrupt received by the interrupt handler is formed into an event message according to a uniform format regardless of the interrupt type or source. The event message includes all information necessary for a host processor interrupt service routine (ISR) to service the interrupts without reading hardware registers. Embodiments include an IO unit interrupt handler that collects all interrupts generated by clients of the IO unit and forms them into event messages. The interrupt handler stores event messages from the input unit into a designated event buffer in memory that is accessible to the host processor, also referred to simply as the host. The interrupt handler also sends an interrupt signal to the host, which responds by reading the event buffer and handling all of the event messages appropriately. The host acknowledges a pulse-based interrupt by updating a read pointer of the event buffer; and acknowledges a level-based interrupt by a register write to clear the interrupt source. In an embodiment, the read pointer is updated by interrupt handler software running on the host after it has read the contents of the event buffer that lie between the current state of the read pointer and the current state of the write pointer. Embodiments further include an adapter unit that receives level-based interrupts from level-based interrupt clients and generates an appropriate event message for storage by the IO unit to the event buffer.

Facts

Application

11/418,788Filed 5 May 2006

Published

US 2007/0260796 A18 Nov 2007

Granted

30 Mar 2010

Term ended

5 May 2026

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification2 codes

G06F 13/24
For access to input/output bus: using interrupt
G06F
Computing and data processing

Event handler for context-switchable and non-context-switchable processing tasks

Life of this patent

Event handler for context-switchable and non-context-switchable processing tasks

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims41

Description7,109 words

Drawings

Classification2 codes

Life of this patent

Description7,109 words