Bus system employing an arbiter
AssigneeInfineon Technologies AG
InventorKarl Herz
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AssigneeInfineon Technologies AG
InventorKarl Herz
Estimating the term…
A method for operating a bus system, in particular in a microprocessor or microcontroller, and a semiconductor device for performing the method is disclosed. In one embodiment, for optimizing the order of accesses to the bus system, a method for operating a bus system includes at least one transmission channel, wherein the transmission channel connects at least two masters and at least one slave with one another. The masters are connected with an arbiter determining the order of accesses in which the masters access the transmission channel. The method provides that the arbiter takes into account meta information about planned accesses when determining the order of accesses. Meta information can further be stored and be referred to for subsequent determinations.
A method for operating a bus, at least two masters, at least one slave, and an arbiter, wherein the at least two masters and the at least one slave are connected with one another via the bus, the method comprising:
A semiconductor device comprising:
A bus system comprising:
A bus system comprising:
Dependencies are inferred from the claim text.
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This Utility Patent Application claims priority to German Patent Application No. DE 10 2006 009 034.9 filed on Feb. 27, 2006, which is incorporated herein by reference.
The invention relates to a method for operating a bus system, in particular in a microprocessor or a microcontroller. Furthermore, the invention relates to a semiconductor device that is suited to perform the method.
In electric or electronic systems, individual system modules communicate via a transmission medium. The system modules may be different electronic devices arranged in a respective component, for instance, different semiconductor devices arranged in a single component. Furthermore, they may be different device sub-components, in particular different components of a semiconductor device, e.g., a memory and/or computing circuit, e.g., a microcontroller or microprocessor, provided in one single device. The transmission medium may, for instance, be a bus or a switch system.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
FIG. 1 illustrates a simplified block diagram of a master-slave communication system;
FIG. 2 illustrates a simplified block diagram of a master-slave system with a switch.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In accordance with one embodiment of the invention there is a method for operating a bus system having at least one transmission channel, wherein the transmission channel connects at least two masters and at least one slave with one another, and wherein the masters are connected with an arbiter that determines the order of access according to which the masters access the transmission channel. When determining the order of access, the arbiter takes into account at least one meta information about at least one access.
A meta information about an access is here information about the access. Thus, a meta information describes or characterizes an access. Relevant meta information about an access is, for instance, the kind of access, i.e. whether it is the matter of a read or write or control access, or the target of the access, e.g., which slave that is connected with the transmission channel is to be accessed. Further meta information may indicate the amount of data to be transmitted with the access, or the—presumable—duration of a planned access.
From the US filing history. Foreign family members aren’t listed.
With centralised access control: using a centralised polling arbiter
Computing and data processing
About 1 year 1 month of term left · ends 4 Dec 2027 (estimated)