Mechanism for synchronizing controllers for enhanced platform power management
AssigneeIntel Corporation
InventorJoseph A. Bennett
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AssigneeIntel Corporation
InventorJoseph A. Bennett
Estimating the term…
In one embodiment, an apparatus to synchronize multiple controllers is disclosed. The apparatus comprises a plurality of controllers, and logic coupled to the plurality of controllers to control one or more controllers of the plurality of controllers to perform fetches simultaneously with one or more other controllers of the plurality of controllers. Other embodiments are also described.
An apparatus, comprising:
A system, comprising:
A method, comprising:
Dependencies are inferred from the claim text.
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Where the bridge performs a synchronising function: where the synchronisation uses buffers, e.g. for speed matching between buses
Monitoring of events, devices or parameters that trigger a change in power modality: monitoring remote activity, e.g. over telephone lines or…
Monitoring of events, devices or parameters that trigger a change in power modality: monitoring of peripheral devices
Energy efficient computing
About 1 year 7 months of term left · ends 23 May 2028 (estimated)
The embodiments of the invention relate generally to the field of platform power management and, more specifically, relate to a mechanism to synchronize multiple controllers.
Presently, chipset implementations may utilize multiple controllers to increase performance. For example, a chipset implementation may include one or more Universal Serial Bus (USB) host controllers. Multiple USB host controllers can increase performance by reducing the amount of USB bandwidth that is shared behind a single controller. Generally, a USB host controller can service two USB ports. With most mobile platforms containing multiple USB ports, these platforms must also contain multiple USB host controllers. Some platforms may have four or five USB host controllers.
Significantly, the operation of each USB host controller is independent from the other USB host controllers (i.e., the state of one has nothing to do with the state of another). Furthermore, the operation of the USB host controllers is periodic. Once started, a USB host controller will fetch a new work list, or frame, every 1 millisecond (ms).
The invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.
FIG. 1A illustrates a block diagram of one embodiment of a computer system;
FIG. 1B illustrates a block diagram of another embodiment of a computer system;
A method and apparatus to synchronize multiple controllers are presented. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the invention.
FIGS. 1A and 1B illustrate a block diagram of one embodiment of a computer system 100. Computer system 100 includes a processor 110 coupled to an interconnect 105. In some embodiments, the terms processor and central processing unit (CPU) may be used interchangeably. In one embodiment, processor 110 is a processor in the Pentium® family of processors including the Pentium® IV processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other processors may be used. In a further embodiment, processor 110 may include multiple processor cores.