US 7,689,741 B2Granted

Dual buffer memory system for reducing data transmission time and control method thereof

AssigneeSamsung Electronics Co., Ltd.

InventorsEun-Suk Kang, Jin-Yub Lee

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Abstract

A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.

Drawings

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Drawings

Claims12

Dependent claims

A memory system comprising:

at least a flash memory block structured to store data;
a flash interface structured to interface with the flash memory block;
a host interface structured to interface with a host;
a first buffer structured to temporarily store data read from the flash memory block or data supplied from the host;
a second buffer structured to temporarily store data read from the flash memory block or data supplied from the host;
a first control circuit structured to receive data read from the flash memory block, a first address, and first control signals through the flash interface or receive input data, a second address, and second control signals applied from the host through the host interface, to select one of the first and second buffers, and to output either the read data, the first address, and the first control signals or the input data, the second address, and the second control signals to the selected buffer;
and a second control circuit structured to receive data output from the first buffer or the second buffer, and output the received data to the flash memory block through the flash interface or to the host through the host interface, wherein, while data stored in one of the first and second buffers is loaded in the flash interface through the second control circuit, simultaneously, data stored in the other one of the first and second buffers is output to the host interface through the second control circuit;
wherein the first control circuit comprises:
a first input selection circuit structured to output read data, a first address, and first control signals received from the flash interface, or to input data, a second address, and second control signals received from the host interface to the first buffer, in response to a first selection signal;
and a second input selection circuit structured to output the read data, the first address, and the first control signals received from the flash interface, or the input data, the second address, and the second control signals received from the host interface to the second buffer, in response to a second selection signal;
wherein the second control circuit comprises:
a first output selection circuit structured to receive data output from the first buffer or the second buffer and output the received data to the host through the host interface, in response to a first selection signal;
and a second output selection circuit structured to receive data output from the first buffer or the second buffer and output the received data to the flash memory block through the flash interface, in response to a second selection signal.

10 more elements

A method of controlling a memory system, the memory system including at least a flash memory block to store data, a flash interface to interface with the flash memory block, a host interface to interface with a host, and first and second buffers to temporarily store data read from the flash memory block and data supplied from the host, the method comprising:

outputting either read data, a first address, and first control signals received from the flash interface, or input data, a second address, and second control signals received from the host interface to the first buffer;
outputting either the read data, the first address, and the first control signals received from the flash interface, or the input data, the second address, and the second control signals received from the host interface to the second buffer;
receiving data output from the first buffer or the second buffer and outputting the received data to the host through the host interface;
and receiving data output from the first buffer or the second buffer and outputting the received data to the flash memory block through the flash interface;
wherein the outputting to the first buffer comprises:
when the host and the flash memory block try to occupy the first buffer at the same time and the flash memory block has a priority lower than the host, blocking the read data, the first address, and the first control signals received from the flash interface and outputting the input data, the second address, and the second control signals received from the host interface to the first buffer;
and when the host and the flash memory block try to occupy the first buffer at the same time and the host has a priority lower than the flash memory block, blocking the input data, the second address, and the second control signals received from the host interface and outputting the read data, the first address, and the first control signals received from the flash interface to the first buffer;
wherein the outputting to the second buffer comprises:
when the host and the flash memory block try to occupy the second buffer at the same time and the flash memory block has a priority lower than the host, blocking the read data, the first address, and the first control signals received from the flash interface and outputting the input data, the second address, and the second control signals received from the host interface to the second buffer;
and when the host and the flash memory block try to occupy the second buffer at the same time and the host has a priority lower than the flash memory block, blocking the input data, the second address, and the second control signals received from the host interface and outputting the read data, the first address, and the first control signals received from the flash interface to the second buffer.

7 more elements

Dependencies are inferred from the claim text.

Description5,863 words

Summary406 words

#This application claims the priority of Korean Patent Application No. 2003-64210, filed on Sep. 16, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

#1. Field of the Invention

#The present invention relates to a memory system, and more particularly, to a dual buffer memory system and a control method thereof.

Brief description of the drawings10 figures

#The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

#FIG. 1 is a block diagram of a dual buffer memory system according to an embodiment of the invention.

#FIG. 2 is a view for explaining an example of a dual buffering method performed by the dual buffer memory system of FIG. 1.

Detailed description5,188 words

#Hereinafter, embodiments of the present invention will be described in detail with reference to the appended drawings.

#The same reference numbers refer to the same components throughout the drawings.

#FIG. 1 is a block diagram of a dual buffer memory system according to an embodiment of the invention. Referring to FIG. 1, the dual buffer memory system includes a flash memory block 11, a flash interface 12, a host interface 13, a first buffer 14, a second buffer 15, a first control circuit 16 and a second control circuit 17.

Facts

Application: 10/940,038Filed 13 Sep 2004
Priority: KR 10-2003-006421016 Sep 2003
Published: US 2005/0060486 A117 Mar 2005
Granted: 30 Mar 2010
Term ends: 29 Oct 2026
Estimated · howhide
20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 776 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification2 codes

G11C 7/1075
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for multiport memories each having random access…
G11C
Static stores

Family

US 2005/0060486 A1Pre-grant publication · published 17 Mar 2005
US 7,689,741 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

16 Sep 2003Priority claimedKR 10-2003-0064210
13 Sep 2004Application filedUS 10/940,038
18 Nov 2004Assigned to Samsung Electronics Co., Ltd.assignment of assignor's interest
17 Mar 2005PublishedUS 2005/0060486 A1
30 Mar 2010GrantedUS 7,689,741 B2
12 Oct 2026TodayWithin its term
29 Oct 2026Term endsEstimated, includes 776 days of adjustment

Citations

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