US 7,689,734 B2 · Method for toggling non-adjacent channel identifiers during DMA double buffering operations

Abstract

Disclosed are a method, a system and a computer program product for managing direct memory access (DMA) operations in a double buffering system. During direct memory access operations in a computer system, data is transferred from a source memory location to a destination memory location with minimal use of the computer's processing unit. Double buffering utilizes two separate memory buffers to perform simultaneous DMA operations. Prior to processing a DMA request each buffer in a double buffering system is assigned a channel identification (ID), or tag. When reading, writing, or polling status of data in a buffer, the tag identifies the buffer. A toggle factor is utilized to conveniently switch between each buffer in the double buffering system. Utilizing a toggle factor decreases latencies in DMA operations.

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Claims17

Dependent claims

In a data processing system supporting DMA data operations via a double buffering DMA system by which two buffers having separate and distinct DMA channels concurrently conduct DMA data operations, a method comprising:

receiving a first DMA tag and a second DMA tag, wherein said first DMA tag and said second DMA tag respectively provide unique labels of a first memory buffer and a second memory buffer of the double buffering DMA system and which associate the first memory buffer and the second memory buffer with a first DMA channel and a second DMA channel;
deterministically toggling between the first memory buffer and the second memory buffer, using the first DMA tag and the second DMA tag, during double buffering DMA data transfer;
wherein the first DMA tag of the first memory buffer includes a first hexadecimal label that identifies the first memory buffer and corresponding first DMA channel;
wherein the second DMA tag of the second memory buffer includes a second hexadecimal label, different from the first hexadecimal label, that identifies the second memory buffer and corresponding second DMA channel;
and
wherein said deterministically toggling further comprises:
performing a first exclusive “OR” operation of the first hexadecimal label and the second hexadecimal label to produce a toggle factor;
performing a second exclusive “OR” operation with the first hexadecimal label of the first memory buffer and the toggle factor to generate the second hexadecimal label of the second memory buffer;
and
performing a third exclusive “OR” operation with the second hexadecimal label of the second memory buffer and the toggle factor to generate the first hexadecimal label of the first memory buffer.

7 more elements

A processor chip comprising:

a processor component;
a DMA controller coupled to the processor component;
logic associated with the DMA controller, which logic performs the functions of:
receiving a first DMA tag and a second DMA tag, wherein said first DMA tag and said second DMA tag respectively provide unique labels of a first memory buffer and a second memory buffer of the double buffering DMA system and which associate the first memory buffer and the second memory buffer with a first DMA channel and a second DMA channel;
deterministically toggling between the first memory buffer and the second memory buffer, using the first DMA tag and the second DMA tag, during double buffering DMA data transfer;
wherein the first DMA tag of the first memory buffer includes a first hexadecimal label that identifies the first memory buffer and corresponding first DMA channel;
wherein the second DMA tag of the second memory buffer includes a second hexadecimal label, different from the first hexadecimal label, that identifies the second memory buffer and corresponding second DMA channel;
and
wherein said logic for deterministically toggling further comprises logic for:
performing a first exclusive “OR” operation of the first hexadecimal label and the second hexadecimal label to produce a toggle factor;
performing a second exclusive “OR” operation with the first hexadecimal label of the first memory buffer and the toggle factor to generate the second hexadecimal label of the second memory buffer;
and
performing a third exclusive “OR” operation with the second hexadecimal label of the second memory buffer and the toggle factor to generate the first hexadecimal label of the first memory buffer.

10 more elements

A data processing system comprising:

a processor;
a memory component coupled to the processor;
a DMA controller coupled to the processor component;
logic associated with the DMA controller, which logic performs the functions of:
receiving a first DMA tag and a second DMA tag, wherein said first DMA tag and said second DMA tag respectively provide unique labels of a first memory buffer and a second memory buffer of the double buffering DMA system and which associate the first memory buffer and the second memory buffer with a first DMA channel and a second DMA channel;
deterministically toggling between the first memory buffer and the second memory buffer, using the first DMA tag and the second DMA tag, during double buffering DMA data transfer;
wherein the first DMA tag of the first memory buffer includes a first hexadecimal label that identifies the first memory buffer and corresponding first DMA channel;
wherein the second DMA tag of the second memory buffer includes a second hexadecimal label, different from the first hexadecimal label, that identifies the second memory buffer and corresponding second DMA channel;
and
wherein said logic for deterministically toggling further comprises logic for:
performing a first exclusive “OR” operation of the first hexadecimal label and the second hexadecimal label to produce a toggle factor;
performing a second exclusive “OR” operation with the first hexadecimal label of the first memory buffer and the toggle factor to generate the second hexadecimal label of the second memory buffer;
and
performing a third exclusive “OR” operation with the second hexadecimal label of the second memory buffer and the toggle factor to generate the first hexadecimal label of the first memory buffer.

11 more elements

Dependencies are inferred from the claim text.

Description3,567 words

Summary602 words

#1. Technical Field

#The present invention generally relates to computer systems and in particular to data transfer in computer memory systems.

#2. Description of the Related Art

Brief description of the drawings5 figures

#The invention itself will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

#FIG. 1 is a block diagram of an example digital signal processor (DSP) with an interconnected DMA (direct memory access) controller according to one embodiment of the invention;

#FIG. 2 is a block diagram illustrating the assignment of tags to memory buffers in a double buffering system;

Detailed description2,822 words

#Disclosed are a method, a system and a computer program product for managing direct memory access (DMA) operations in a double buffering system. During direct memory access operations in a computer system, data is transferred from a source memory location to a destination memory location with minimal use of the computer's processing unit. Double buffering utilizes two separate memory buffers to perform simultaneous DMA operations. Prior to processing a DMA request, each buffer in a double buffering system is assigned a channel identification (ID), or tag. When reading, writing, or polling status of data in a buffer, the tag identifies the buffer. A toggle factor is utilized to conveniently switch between each buffer in the double buffering system. Utilizing a toggle factor decreases latencies in DMA operations.

#In the following detailed description of exemplary embodiments of the invention, specific exemplary embodiments in which the invention may be practiced are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, architectural, programmatic, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

#Within the descriptions of the figures, similar elements are provided similar names and reference numerals as those of the previous figure(s). Where a later figure utilizes the element in a different context or with different functionality, the element is provided a different leading numeral representative of the figure number (e.g, 1xx for FIG. 1 and 2xx for FIG. 2). The specific numerals assigned to the elements are provided solely to aid in the description and not meant to imply any limitations (structural or functional) on the invention.

Facts

Application

11/958,642Filed 18 Dec 2007

Published

US 2009/0157913 A118 Jun 2009

Granted

30 Mar 2010

Term ends

13 Apr 2028

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 117 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification2 codes

G06F 13/28
For access to input/output bus: using burst mode transfer, e.g. direct memory access DMA, cycle steal
G06F
Computing and data processing

Timeline

18 Dec 2007Application filedUS 11/958,642
18 Dec 2007Assigned to International Business Machines Corporationassignment of assignor's interest
18 Jun 2009PublishedUS 2009/0157913 A1
30 Mar 2010GrantedUS 7,689,734 B2
12 Oct 2026TodayWithin its term
13 Apr 2028Term endsEstimated, includes 117 days of adjustment

Method for toggling non-adjacent channel identifiers during DMA double buffering operations

Life of this patent

Method for toggling non-adjacent channel identifiers during DMA double buffering operations

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims17

Description3,567 words

Drawings

Classification2 codes

Life of this patent

Description3,567 words