Method for implementing resets in two computers

#The present invention relates to a method for implementing a reset in both a master computer and an associated slave computer which are both connected to a common data bus. Furthermore, the present invention relates to a computer program and a master computer for implementing this method.

#It is known from the related art that both a master computer and a slave computer can be connected to a shared data bus. In such a hardware constellation the two computers must generally be configurable with different reset configurations, which hereinafter will be referred to as master-reset configuration and slave-reset configuration, respectively. As a rule, the two computers have internal memories via which internal standard reset configurations can be called up. However, due to the mentioned hardware constellation, it is possible that the internal reset configuration cannot be utilized in any of the two computers, or at least in the slave computer. This will then have the disadvantage that a shared operation of both master computer and slave computer on the shared data bus is impossible.

#Proceeding from this related art, it is an objective of the present invention to further develop a known method for implementing a reset both in a master computer and in a slave computer which are both connected to a common data bus, namely in such a manner that the master and the slave computer are configurable with different reset configurations notwithstanding the fact that the slave computer, in particular, cannot implement an internal slave-reset configuration.

#FIG. 1 shows a hardware constellation on which the present invention is based.

#FIG. 2 shows the profile of a reset signal.

#FIG. 3 shows the method according to the present invention.

#FIG. 1 shows the hardware constellation on which the present invention is based as it may be provided in a control unit, for example. This hardware constellation includes a master computer 110 and a slave computer 120, which are both connected to a shared data bus 130. Moreover, the two computers 110, 120 are connected to a shared address bus 132, a shared control bus 134 and also to a shared timing circuit 136. In addition, according to the present invention, a first port a of master computer 110 is designed to output to slave computer 120 a reset-release signal that indicates the end of the master configuration. Furthermore, according to the present invention a second port b of master computer 110 is provided and designed to output to slave computer 120 a data-bus release signal that indicates the release of the data bus to normal data traffic after the slave-reset configuration has been concluded. Both master computer 110 and slave computer 120 are microcontrollers, for instance.

#Finally, the hardware constellation includes a reset generator 140 for generating a reset signal and for outputting this reset signal to master computer 110.

#FIG. 2 illustrates typical profiles of digital reset signal SR and a supply voltage U for a computer, regardless of whether the computer is operated as master or slave.