SIMD integer multiply high with round and shift

A method comprising:

• receiving a single instruction to cause a hardware execution unit of a microprocessor to perform a packed multiply high with round and shift operation on two operands in response to the single instruction, wherein said packed multiply with round and shift operation comprises
• multiplying each data element in a first set of packed data elements with a corresponding data element in a second set of packed data elements to generate a set of products,
• rounding and shifting each of said set of products to generate a set of results, and
• selecting a plurality of bits from each of said results to generate a set of truncated results;
• said single instruction having a format comprising:
• a first field that has stored therein an op code that specifies said packed multiply with round and shift operation and whether said set of truncated results for said packed multiply high with round and shift operation is comprised of high order bits or low order bits of said set of results;
• a second field that has stored therein data that specifies a first source address for a first operand having said first set of packed data elements;
• and
• a third field that has stored therein data that specifies a second source address for a second operand having said second set of packed data elements;
• and
• executing said single instruction at the hardware execution unit of the microprocessor to generate said set of truncated results for;
• and
• storing said set of truncated results as packed data elements in a destination register as a final result.

An apparatus comprising:

• a hardware execution unit of a microprocessor to perform a packed multiply with round and shift operation responsive to a single instruction, wherein said execution unit in response to only said single instruction is to,
• multiply each data element in a first set of packed data elements with a corresponding data element in a second set of packed data elements to generate a set of products,
• round each of said set of products to generate a set of results
• shift each of said set of results to generate an intermediate set of results,
• select a plurality of bits from each of said results to generate a set of truncated results, and
• store said set of truncated results as a final result,
• wherein said single instruction having a format comprising:
• a first field to specify an op code to provide information about said packed multiply with round and shift operation, wherein said op code is to indicate whether said set of truncated results for said packed multiply high with round and shift operation is comprised of high order bits or low order bits of said set of results,
• a second field to specify a first source address for a first operand having said first set of packed data elements, and
• a third field to specify a second source address for a second operand having said second set of packed data elements.

A system comprising:

• a memory to store a first instruction;
• and
• a processor to fetch the first instruction from the memory and, in response to executing the first instruction, the processor is to:
• multiply each data element in a first set of packed data elements with a corresponding data element in a second set of packed data elements to generate a set of products,
• round each of said set of products to generate a set of temporary results,
• scale each of said set of temporary results to generate a set of scaled temporary results,
• select a plurality of bits from each of said scaled temporary results to generate a set of truncated results, and
• store said set of truncated results as a final result;
• and
• wherein said first instruction has a format comprising:
• a first field to specify an op code to provide information about said packed multiply with round and shift operation, wherein said information of said op code indicates a packed multiply with round and shift of signed integers and to select high order bits of each of said results for a truncated result,
• a second field to specify a first source address for a first operand having said first set of packed data elements, and
• a third field to specify a second source address for a second operand having said second set of packed data elements.

A machine readable storage medium storing a program, said program being executable by a computer system to perform a method comprising:

• responsive to executing a single instruction, wherein the single instruction designates a first operand at a first storage register having a first set of L data elements and a second operand at a second storage register having a second set of L data elements, the computer system performing the following acts,
• multiplying together L pairs of data elements to generate a set of L products, wherein each of said L pairs includes a first data element from said first set of L data element and a second data element from a corresponding data element position of said second set of L data elements;
• shifting each of said L products to generate L shifted values;
• rounding each of said L shifted values to generate L rounded values;
• scaling each of said L rounded values to generate L scaled values;
• truncating each of said L scaled values for storage at a destination by selecting sixteen least significant bits from each of said L scaled values to obtain L truncated values, wherein each truncated value is to be stored at a data element position corresponding to its pair of data elements;
• and
• storing each of said L truncated values as a final result at a destination storage register.

A machine readable storage medium storing a program, said program being executable by a computer system to perform a method comprising:

• responsive to executing a single instruction, the computer system performing the following acts,
• multiplying each data element in a first operand with a corresponding data element in a second operand to generate a set of products,
• rounding each of said set of products to generate a set of rounded intermediate results,
• shifting each of said set of rounded intermediate results to generate a set of scaled results,
• selecting a plurality of bits from each of said scaled results to generate a set of resultant data elements, and
• storing said set of resultant data elements as a final result,
• said single instruction having a format comprising:
• a first field that has stored therein an op code that specifies said packed multiply with round and shift operation and whether said set of truncated results for said packed multiply high with round and shift operation is comprised of high order bits or low order bits of said set of results;
• a second that has stored therein data that specifies a first source address for a first operand having said first set of packed data elements;
• and
• a third field that has stored therein data that specifies a second source address for a second operand having said second set of packed data elements.