Pipeline processing system and information processing apparatus

An information processing apparatus for reading recorded data from a recording medium of a predetermined format, comprising:

• a demodulation circuit operating as a pipeline processing stage demodulating data;
• an error processing circuit operating as a pipeline stage and performing predetermined error processing on data output from said demodulation circuit;
• a plurality of memories, each able to store data each having a capacity required in at least each pipeline stage and accessed by any circuit of said demodulation circuit or the error processing circuit;
• and
• a first bus for switching data paths between said demodulation circuit and error processing circuit and the plurality of memories in accordance with predetermined status information and transferring data among pipeline stages;
• and
• further comprising a buffer memory connected to at least one of the plurality of pipeline processing stages via a second bus, wherein each of the pipeline processing stases is capable of performing its distinct processing on a block of data simultaneously while the remaining processing circuits are also processing a similar size block of data.

An information processing apparatus for recording input data in a recording medium, comprising:

• a recording data preparation circuit operating as a pipeline stage and preparing the data to be recorded;
• a modulation circuit operating as a pipeline stage, modulating said prepared recording data, and outputting the same as the recording data;
• a plurality of memories able to store the data having a capacity required in at least each pipeline stage and accessed by any of said modulation circuit or recording data preparation circuit;
• and
• a first bus for switching data paths between said modulation circuit and recording data preparation circuit and the plurality of memories in accordance with predetermined status information and transferring data among pipeline stages;
• and
• further comprising a buffer memory connected to at least one of the plurality of pipeline stages via a second bus, wherein each of the pipeline stages is capable of performing its distinct processing on a block of data simultaneously while the remaining pipeline processing stages are also processing a similar size block of data.

An information processing apparatus for reading recording data from a recording medium of a predetermined format and recording input data as data of a predetermined format in the recording medium, comprising:

• a demodulation circuit operating as a pipeline stage and demodulating read data;
• an error processing circuit operating as a pipeline stage and performing predetermined error processing on the data after said demodulation;
• a recording data preparation circuit operating as a pipeline stage and preparing data to be recorded;
• a modulation circuit operating as a pipeline stage, modulating said prepared recording data, and outputting the same as the recording data;
• a plurality of memories each able to store data having a capacity required in at least said each pipeline stage and accessed by any of said demodulation circuit, error processing circuit, recording data preparation circuit, and modulation circuit;
• and
• a first bus switching data paths between said demodulation circuit and error processing circuit or said recording data preparation circuit and modulation circuit and the plurality of memories in accordance with predetermined status information;
• and
• further comprising a buffer memory connected to at least one of the plurality of processing circuits via a second bus, wherein each of the pipeline stages is can able of performing its distinct processing on a block of data simultaneously while the remaining pipeline processing stages are also processing a similar size block of data.