A rijndael block cipher apparatus having M-bit input data and N-bit input keys, and encrypting the M-bit input data by repeating for a predetermined number of times a round operation for encryption that includes transforms of shift_row, substitution, mixcolumn and add-round-key or decrypting the M-bit input data by repeating for a predetermined number of times a round operation for decryption that includes transforms of inverse shift_row inverse substitution, add-round-key and inverse mixcolumn, the apparatus comprising:
- a round operation unit including a round operation execution unit for processing the data in the unit of M/m bits (where m is 2, 3 or 4) at least in the transforms of substitution, mixcolumn and add-round-key in an encryption mode and for processing the data in the unit of M/m bits (where m is 2, 3 or 4) at lease in the transforms of inverse substitution, add-round-key and inverse mixcolumn in a decryption mode, and a round key generation unit for generating round keys in order to provide the round keys in the transform of add-round-key;
- a round operation control unit for controlling the round operation performed by the round operation unit;
- and
- a data storage unit for storing M/m-bit intermediate data generated by the round operation unit at an intermediate stage of every round and M-bit data generated at an end stage of every round,
- wherein the round keys generated in the round key generation unit is added to an upper M/m input data in the round operation execution unit while simultaneously begin processing of a lower M/m input data in the round operation execution unit before the end stage of every round for the upper M/m input data in the round operation execution unit at a same clock cycle without the upper M/m input data and the lower M/m input being processed in any one of a same transform of the transforms comprising of at least the substitution, mixcolumn and add-round-key,
- wherein the end stage of every round indicates that the data in the unit of M/m bits (where m is 2, 3 or 4) have been processed in all of the at least transforms of the substitution, mixcolumn and add-round-key, and
- wherein the processing of the upper M/m input data and the lower M/m input data are transformed in a same manner of a same circuit for each of the at least transforms of the substitution, mixcolumn and add-round-key.