Method and system for implementing FO function in KASUMI algorithm for accelerating cryptography in GSM (global system for mobile communication)GPRS (general packet radio service)edge(enhanced data rate for GSM evolution) compliant handsets

A system for accelerating cryptography operations, the system comprising:

• one or more circuits that are adapted to generate at least a first indicator that indicates completion of a round of a Kasumi FI processing when cryptographically processing information;
• said one or more circuits are adapted to transfer a first output generated from a first round of said Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register;
• said one or more circuits are adapted to XOR a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output;
• and
• said one or more circuits are adapted to clock said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first indicator indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing.

A method for accelerating cryptography operations, the method comprising:

• performing by one or more processors and/or circuits integrated within a single chip:
• generating at least a first signal that indicates completion of a round of a Kasumi FI processing when cryptographically processing information;
• transferring a first output generated from a first round of said Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register;
• XORing a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output;
• clocking said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first signal indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing;
• and
• feeding back said first output generated from said first round of said Kasumi FI processing to generate said second output generated from said second round of said Kasumi FI processing.

A method for accelerating cryptography operations, the method comprising:

• performing by one or more processors and/or circuits integrated within a single chip:
• generating at least a first signal that indicates completion of a round of a Kasumi FI processing when cryptographically processing information;
• transferring a first output generated from a first round of said Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register;
• XORing a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output;
• clocking said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first signal indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing;
• and
• feeding back said second output generated from said second round of said Kasumi FI processing to generate said third output generated from said third round of said Kasumi FI processing.

A method for accelerating cryptography operations, the method comprising:

• performing by one or more processors and/or circuits integrated within a single chip:
• generating at least a first signal that indicates completion of a round of a Kasumi FI processing when cryptographically processing information;
• transferring a first output generated from a first round of said Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register;
• XORing a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output;
• clocking said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first signal indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing;
• and
• generating a first Kasumi FI input during said first round of said Kasumi FI processing by XORing a first subkey and a first portion of an input data in a pipeline state machine.

A system for accelerating cryptography operations, the system comprising:

• one or more circuits that are adapted to generate at least a first indicator that indicates completion of a round of a Kasumi FI processing when cryptographically processing information;
• said one or more circuits are adapted to transfer a first output generated from a first round of a Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register;
• said one or more circuits are adapted to XOR a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output;
• said one or more circuits are adapted to clock said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first indicator indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing;
• and
• said one or more circuits are adapted to feedback said first output generated from said first round of said Kasumi FI processing to generate said second output generated from said second round of said Kasumi FI processing.

A system for accelerating cryptography operations, the system comprising:

• one or more circuits that are adapted to generate at least a first signal indicator;
• said one or more circuits are adapted to transfer a first output generated from a first round of a Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register;
• said one or more circuits are adapted to XOR a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output;
• said one or more circuits are adapted to clock said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first indicator indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing;
• and
• said one or more circuits are adapted to feedback said second output generated from said second round of said Kasumi FI processing to generate said third output generated from said third round of said Kasumi FI processing.

A system for accelerating cryptography operations, the system comprising:

• one or more circuits that are adapted to generate at least a first indicator that indicates completion of a round of a Kasumi FI processing when cryptographically processing information;
• said one or more circuits are adapted to transfer a first output generated from a first round of a Kasumi FI processing and a second output generated from a second round of said Kasumi FI processing to a pipeline register;
• said one or more circuits are adapted to transfer a third output generated from a third round of said Kasumi FI processing with said second output generated from said second round of said Kasumi FI processing to generate a first portion of an Kasumi FI generated output;
• said one or more circuits are adapted to clock said second output generated from said second round of said Kasumi FI processing from said pipeline register to generate a second portion of said Kasumi FI generated output, after said at least said first indicator indicates that said second round of said Kasumi FI processing is complete, wherein resulting information from said cryptographic processing is communicated to a remote location for further processing;
• and
• said one or more circuits are adapted to generate a first Kasumi FI input during said first round of said Kasumi FI processing by XORing a first subkey and a first portion of an input data in a pipeline state machine.