Shift register circuit and display drive device

A shift register circuit comprising:

• plural stages of signal holding circuits which are supplied with an input signal, and are cascade-connected to output an output signal based on the input signal and to supply the output signal as an input signal to a subsequent stage,
• wherein each of the plural stages of signal holding circuits is supplied with two types of clock signals comprising a first clock signal and a second clock signal, wherein a rise timing of the second clock signal between the fall timing of the first clock signal to the rise timing thereof, a reset signal, and is supplied with the input signal in synchronization with the fall timing of the first clock signal, and wherein each of the plural stages of signal holding circuits comprises:
• (i) a latch circuit which holds the input signal at a timing delayed by a delay time from the timing of applying the input signal to the rise timing of the second clock signal in response to the second clock signal and resets the held input signal in response to the reset signal;
• and
• (ii) an output circuit which outputs the held input signal as the output signal at a timing in response to the first clock signal.

A shift register circuit comprising:

• plural stages of signal holding circuits which are supplied with an input signal, and are cascade-connected to output an output signal based on the input signal and to supply the output signal as the input signal to a subsequent stage,
• wherein each of the plural stages of signal holding circuits is supplied with two types of clock signals comprising a first clock signal and a second clock signal, wherein a rise timing of the second clock signal is between the fall timing of the first clock signal and the rise timing thereof, a reset signal, and is supplied with the input signal in synchronization with the fall timing of the first clock signal and wherein each of the plural stages of signal holding circuits comprises:
• (i) a latch circuit which holds the input signal and resets the held input signal in response to the reset signal;
• and
• (ii) an output circuit which outputs the held input signal as the output signal wherein the held signal is supplied to the output circuit at a timing delayed by the delay time from the timing of applying the input signal to the rise timing of the second clock signal, at a timing delayed by the delay time from the timing of applying the input signal to the rise timing of the second clock signal in response to the second clock signal.

A shift register circuit comprising:

• plural stages of signal holding circuits which are cascade-connected to hold a first signal based on a supplied input signal, to output an output signal based on the held first signal, and to supply the output signal as the input signal to a subsequent stage;
• wherein each of the plural stages of signal holding circuits comprises an output circuit which:
• (i) is supplied with two types of clock signals further comprising a first clock signal and a second clock signal, wherein a rise timing of the second clock signal is between a fall timing of the first clock signal and a rise timing thereof, (ii) is supplied with the input signal in synchronization with the fall timing of the first clock signal, (iii) is supplied with a second signal at a timing delayed by a delay time from a timing of applying the input signal to the rise timing of the second clock signal, and (iv) outputs the output signal at a timing in response to the first clock signal;
• wherein the output circuit has at least one transistor, and the transistor is turned ON only between a timing delayed by the delay time from the timing of applying the input signal and a timing at which the reset signal is applied.