Detection of a digital counter malfunction
AssigneeSTMicroelectronics S.r.l.
InventorPhilippe Roquelaure
Life of this patent
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Abstract
A method and a circuit for detecting a malfunction of at least one first counter controlled by a first signal, in which a second counter, controlled by a second signal identical to the first signal or to its inverse, and counting in the reverse direction with respect to the first counter, is set with a value complementary to a setting value of the first counter; the respective current values of the first and second counters are added up; and the current sum is compared with at least one value representing the greatest one of the setting values or this greatest value plus one.
Claims17
A method for detecting a malfunction of at least one first counter controlled by a first signal, the method comprising:
- setting a second counter controlled by a second signal identical to the first signal or to its inverse, and counting in a reverse direction with respect to the first counter, with a value complementary to a setting value of the first counter;
- adding respective current values of the first and second counters;
- and
- comparing a current sum with at least one value representing a greatest one of the setting values or this greatest value plus one.
A circuit for detecting a malfunction of a first counter controlled by a first signal, the circuit comprising:
- a second counter controlled by a second signal identical to the first signal or to its inverse and structured to vary in a reverse direction with respect to the at least one counter;
- an adder structured to add respective current values of the first and second counters;
- and
- at least one comparator structured to compare a result provided by the adder with respect to a greatest value of two respective complementary setting values of the counters or to this greatest value plus one.
An electronic circuit, comprising:
- a first counter controlled by a first signal;
- and
- a detection circuit structured to detect a malfunction of said first counter, the detection circuit including:
- a second counter structured to be controlled by a second signal identical to the first signal or to its inverse, and structured to count in a reverse direction with respect to first counter;
- an adder coupled to said first and second counters, and structured to add respective current values of the first and second counters;
- and
- at least one comparator coupled to said adder, and structured to compare a result provided by the adder to a maximum value of the counters or to this maximum value plus one, wherein said malfunction is detected if said comparison indicates an inequality between said result and said maximum value or said maximum value plus one.
A method for detecting a malfunction of a first counter controlled by a first signal, the method comprising:
- setting a second counter, controlled by a second signal identical to the first signal or to its inverse, to count in a reverse direction with respect to the first counter, a maximum value of the first and second counters being identical;
- adding respective current values of the first and second counters to obtain a current sum;
- comparing said current sum to said maximum value or to said maximum value plus one;
- and
- determining that said malfunction exists is said comparing indicates that said current sum is unequal to said maximum value or to said maximum value plus one.
Dependencies are inferred from the claim text.