All-digital phase modulator/demodulator using multi-phase clocks and digital PLL

A de-modulator comprising:

• a phase comparator, receiving a phase-modulated signal transmitted over a communications medium, and receiving a feedback clock, for detecting a phase difference between the phase-modulated signal and the feedback clock;
• an up/down counter, responsive to the phase difference from the phase comparator, for incrementing or decrementing a count value in response to the phase difference being positive or negative;
• a plurality of multi-phase clocks having a same frequency but being offset in phase from one another;
• a phase rotator, receiving the plurality of multi-phase clocks, for selecting as a rotated clock one of the plurality of multi-phase clocks in response to the count value from the up/down counter;
• a divider, receiving the rotated clock from the phase rotator, for generating the feedback clock by dividing the rotated clock by a divisor;
• and
• a converter, receiving the count value from the up/down counter, for generating a demodulated output signal that represents phase encodings of the phase-modulated signal,
• whereby the demodulated output signal is generated from the count value that controls selection of the rotated clock from among the plurality of multi-phase clocks in response to phase comparison of the phase-modulated signal.

A phase modulator selecting multi-phase clocks comprising:

• multi-phase clock generator means, receiving a reference clock, for generating a plurality of multi-phase clocks having a phase-clock frequency but different phases;
• input sampling means, receiving an input signal for encoding as a phase-encoded signal, for generating a counter-control signal synchronized to a feedback clock;
• counter means, responsive to the counter-control signal, for incrementing and decrementing a count value;
• phase select means, responsive to the count value from the counter means, for selecting as a rotated clock one of the plurality of multi-phase clocks in response to the count value;
• output divider means, receiving the rotated clock from the phase select means, for generating the phase-encoded signal as an output;
• feedback divider means, receiving a fixed-phase clock having the phase-clock frequency and a phase that does not vary with the count value, for generating the feedback clock;
• wherein the input sampling means comprises a bit-map means for convening multi-bit sequences of digital bits on the input signal to the counter-control signal,
• or wherein the input sampling means comprises an analog front end that comprises:
• voltage compare means, receiving the input signal as an analog voltage, for comparing an accumulated feedback voltage to the input signal to generate the counter-control signal;
• latch means, clocked by the feedback clock, for sampling the counter-control signal to generate a sampled signal;
• and
• accumulate means, receiving the sampled signal, for generating the accumulated feedback voltage by accumulating the sampled signal over several cycles of the feedback clock,
• whereby the input signal is sampled to increment and decrement the counter means and select a phase from the plurality of multi-phase clocks to generate the phase-encoded signal from the input signal.