Duty cycle counting phase calibration scheme of an input/output (I/O) interface

A control unit comprising:

• a first-PLL to generate a set of un-calibrated multiple-phase signals of a first-clock such that each signal in the set of un-calibrated multiple-phase signals of the first-clock has a periodic repetition rate of a first-clock-frequency of the first-clock and includes a logically critical voltage transition edge;
• a second-PLL to generate a second-clock with a second-clock-frequency which is different from the first-clock-frequency in a predetermined amount;
• a pulse generator to logically combine the signals in the set of un-calibrated multiple-phase signals of the first-clock to generate a set of pulsed signals;
• a pulse-width measurement unit to measure a pulse width of the signals in the set of pulsed signals utilizing plurality of time periods of the second-clock;
• a phase calibration engine to evaluate adjustments required in a temporal location of the logically critical voltage transition edge in each signal in the set of un-calibrated multiple-phase signals of the first-clock;
• and
• a phase adjustment unit to adjust the temporal location of the logically critical voltage transition edge in each signal in the set of un-calibrated multiple-phase signals of the first-clock to generate a set of calibrated multiple-phase signals of the first-clock such that each signal in the set of calibrated multiple-phase signals of the first-clock includes the logically critical voltage transition edge which is time skewed in a predetermined amount from the logically critical voltage transition edge in other signals in the same set within a predetermined accuracy.

A method, comprising:

• generating a set of un-calibrated multiple-phase signals of a first-clock using a first-PLL such that each signal in the set of un-calibrated multiple-phase signals of the first-clock has a periodic repetition rate of a first-clock-frequency of the first-clock and includes a logically critical voltage transition edge;
• generating a second-clock with a second-clock-frequency which is different from the first-clock-frequency in a predetermined amount using a second-PLL;
• generating a set of pulsed signals by logically combining the signals in the set of un-calibrated multiple-phase signals of the first-clock using a multiplexer and an AND gate of a pulse generator circuit;
• measuring a pulse width of the signals in the set of pulsed signals utilizing plurality of time periods the second-clock using a pulse width measurement unit;
• evaluating adjustments required in a temporal location of the logically critical voltage transition edge in each signal in the set of un-calibrated multiple-phase signals of the first-clock using a phase calibration engine;
• and
• generating a set of calibrated multiple-phase signals of the first-clock by adjusting the temporal location of the logically critical voltage transition edge in each signal in the set of un-calibrated multiple-phase signals of the first-clock such that each signal in the set of calibrated multiple-phase signals of the first-clock includes the logically critical voltage transition edge which is time skewed in a predetermined amount from the logically critical voltage transition edge in other signals in the same set within a predetermined accuracy using a phase adjustment unit.