Parallel samples, parallel coefficients, time division multiplexing correlator architecture

A method for managing a code sequence, comprising:

• processing a first group of coefficients in the code sequence, loaded in a plurality of code sequence registers during a first clock cycle, with a first group of contiguous sample values, loaded in a plurality of sample sequence registers, in a received sample to determine a first intermediate correlation value during the first clock cycle;
• processing a second group of coefficients in the code sequence, loaded in the plurality of code sequence registers previously used for the first group of coefficients during a second clock cycle, with a second group of contiguous sample values, loaded in the plurality of sample sequence registers, in the received sample to determine a second intermediate correlation value during the second clock cycle;
• determining a correlation output from the first and second intermediate correlation values;
• and
• determining a synchronization point that identifies an amount of delay incurred from transmission of the sample values from the correlation output.

A method for managing a code sequence, comprising:

• organizing the code sequence, having L contiguous coefficients, into L/n contiguous code sequence groups having n coefficients each, wherein n and L are greater than 1;
• selecting a number of sample sequences to process in parallel where each of the sample sequences has contiguous sample values from a received sample;
• organizing contiguous sample values from each of a first set of contiguous sample sequences to process in parallel into a first set of contiguous sample sequence groups;
• processing coefficients in each of the code sequence groups loaded into a plurality of code sequence registers in parallel with corresponding sample values in corresponding sample sequence groups from the first set of sample sequences loaded into a plurality of sample sequence registers, where each of code sequence groups is processed during a different clock cycle;
• determining a correlation output for each of the sample sequences;
• and
• determining a synchronization point that identifies an amount of delay incurred from transmission of the sample sequences from the correlation output.

A method for managing a code sequence, comprising:

• organizing the code sequence, having L contiguous coefficients, into L/n contiguous code sequence groups having n coefficients each, wherein n and L are greater than 1;
• selecting a number of sample sequences, d, to process in parallel where each of the sample sequences has L contiguous sample values from a received sample, where a first sample value in a first sample sequence is a first sample value in the received sample and each consecutive sample sequence includes a next contiguous sample value in the received sample as a first sample value in the consecutive sample sequence;
• organizing sample values from each of a first set of d sample sequences into a first set of sample sequence groups having n values each and loading the set into a plurality of sample sequence registers;
• processing coefficients in each of the code sequence groups loaded into a plurality of code sequence registers in parallel with corresponding sample values in corresponding sample sequence groups from the first set of d sample sequences, where each of the code sequence groups is processed during a different clock cycle, where d may be any value;
• determining a correlation output for each of the sample sequences;
• and
• determining a synchronization point that identifies an amount of delay incurred from transmission of the sample sequences from the correlation output.

A correlator unit, comprising:

• a plurality of code sequence registers that store coefficients from a code sequence group having n coefficients, the plurality of code sequence registers storing coefficients from one code sequence group of L/n code sequence groups at a time, where L is the number of coefficients in a code sequence, wherein n and L are greater than 1;
• a plurality of sample registers that store sample values from a plurality of sample sequences that are processed in parallel;
• a processing unit that processes coefficients in each of the plurality of code sequence groups in the plurality of code sequence registers in parallel with corresponding sample values in corresponding sample sequence groups from a first plurality of sample sequences in the plurality of sample registers, where each of the code sequence groups is processed to generate intermediate correlation values during a different clock cycle;
• an accumulation unit that generates a correlation output for each of the sample sequences from the intermediate correlation values generated during the different clock cycles;
• and
• a correlation output processor that determines a synchronization point that identifies an amount of delay incurred from transmission of the sample sequences from the correlation output.

A correlator unit, comprising:

• a plurality of n code sequence registers that store n coefficients from a code sequence group, the plurality of n code sequence registers storing coefficients from one code sequence group of L/n code sequence groups at a time, where L is the number of coefficients in a code sequence, wherein n and L are greater than 1;
• a plurality of n+d−1 sample registers that store sample values from a plurality of d sample sequences that are processed in parallel, wherein d is greater than 1;
• and
• a processing unit that processes coefficients in each of the plurality of code sequence groups in the plurality of n code sequence registers in parallel with corresponding sample values in corresponding sample sequence groups from a first plurality of d sample sequences in the plurality of n+d−1 sample registers, where each of the code sequence groups is processed to generate intermediate correlation values during a different clock cycle, wherein d may be any value;
• an accumulation unit that determines a correlation output for each of the sample sequences from the intermediate correlation values generated during the different clock cycles;
• and
• a correlation output processor to determine a synchronization point that identifies an amount of delay incurred from transmission of the sample sequences from the correlation output.

A correlator unit, comprising:

• means for storing coefficients from a code sequence group having n coefficients, the means for storing coefficients from one code sequence group of L/n code sequence groups at a time, where L is a number of coefficients in a code sequence, wherein n and L are greater than 1;
• means for storing sample values from a plurality of sample sequences that are processed in parallel;
• means for processing coefficients in each of the plurality of code sequence groups in the means for storing coefficients in parallel with corresponding sample values in corresponding sample sequence groups from a first plurality of contiguous sample sequences in the means for storing sample values, where each of the code sequence groups is processed to generate intermediate correlation values during a different clock cycle;
• means for determining a correlation output for each of the sample sequences from the intermediate correlation values generated during the different clock cycles;
• and
• means for determining a synchronization point that identifies an amount of delay incurred from transmission of the sample sequences from the correlation output.