Semiconductor package having dimpled plate interconnections
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsMing Sun, Lei Shi, Kai Liu
Life of this patent
Estimating the term…
Abstract
A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.
Claims12
A semiconductor package comprising:
- a leadframe having drain, source and gate leads;
- a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area;
- a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, the dimples being positioned for contact with the metalized source areas;
- a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, the dimple being positioned for contact with the metalized gate area;
- a semiconductor die drain area coupled to the drain lead;
- and
- an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.
A semiconductor package comprising:
- a leadframe having drain, source and gate leads;
- a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of Ni/Au metalized source areas and a Ni/Au metalized gate area;
- a patterned source connection having a plurality of dimples formed thereon, the plurality of dimples coupling the source lead to the semiconductor die metalized source areas in corresponding relationship therewith, the patterned source connection being soldered to the semiconductor die metalized source areas;
- a semiconductor die drain area coupled to the drain lead;
- and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.
Dependencies are inferred from the claim text.