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US 7,682,988 B2Granted
Thermal treatment of nitrided oxide to improve negative bias thermal instability
AssigneeTexas Instruments Incorporated
InventorsHusam N. Alshareef, Rajesh Khamankar, Ajith Varghese, Cathy A. Chancellor, Anand Krishnan, Malcolm J. Bevan
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Abstract
A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
Claims21
A method of manufacturing a semiconductor device, comprising:
- forming a nitrided dielectric layer on a semiconductor substrate;
- and
- subjecting the nitrided dielectric layer to an anneal at low pressure in an ambient that substantially excludes nitrogen.
A method of manufacturing an integrated circuit, comprising:
- forming a nitrided gate dielectric layer on a semiconductor substrate;
- subjecting the nitrided gate dielectric layer to an anneal at low pressure in an ambient that substantially excludes nitrogen to form an annealed gate dielectric layer;
- forming a gate layer over the annealed gate dielectric layer;
- forming wells and source/drains in the semiconductor substrate;
- patterning the gate layer and the annealed gate dielectric layer to form transistor gates;
- placing dielectric layers over the transistor gates;
- and
- forming interconnects in the dielectric layers that interconnect the transistor gates to form an operative integrated circuit.
5 more elements
Dependencies are inferred from the claim text.