Advanced multilayer coreless support structures and method for their fabrication
AssigneeAmitec-Advanced Multilayer Interconnect Technoloiges Ltd.
InventorsDror Hurwitz, Mordechay Farkash, Eva Igner, Boris Statnikov, Benny Michaeli
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Abstract
A method of fabricating a free standing membrane including via array in a dielectric for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing laminated array, followed by terminating.
Claims22
A method of fabricating a free standing membrane comprising a via array in a dielectric surround comprising polymer, for use as a precursor in the construction of superior electronic support structures, comprising the stages:
- I—fabricating a membrane comprising conductive vias in a dielectric surround comprising polymer on a sacrificial carrier, comprising the sub-steps of:
- (i) panel plating a barrier metal layer onto a sacrificial carrier;
- (ii) applying a seed layer of copper onto the barrier metal layer;
- (iii) applying, exposing and developing a photoresist layer onto the copper seed layer to form patterns;
- (iv) pattern plating copper vias into the photo resist patterns;
- (v) stripping away the photoresist layer leaving the upstanding copper vias, and
- (vi) laminating a dielectric material layer over the copper vias, such that the free standing membrane formed thereby comprises a copper via array in a dielectric matrix;
- and
- II—detaching the membrane from the sacrificial carrier to form a free standing laminated array.
A method of fabricating an electronic substrate comprising at least the stages of:
- I—fabricating a membrane comprising conductive vias in a dielectric surround comprising polymer on a sacrificial carrier, comprising the sub-steps of:
- (i) panel plating a barrier metal layer onto a sacrificial carrier;
- (ii) applying a seed layer of copper onto the barrier metal layer;
- (iii) applying, exposing and developing a photoresist layer onto the copper seed layer to form patterns;
- (iv) pattern plating copper vias into the photoresist patterns;
- (v) stripping away the photoresist layer leaving the upstanding copper vias, and
- (vi) laminating a dielectric material layer over the copper vias;
- II—detaching the membrane from the sacrificial carrier to form a free standing laminated array, comprising the sub steps of:
- (vii) removing the sacrificial carrier, and
- (viii) removing the barrier metal layer;
- V—thinning and planarizing;
- VI—building-up;
- and
- VII—terminating,
- such that the resulting electronic substrate comprises a copper structure in a dielectric matrix.
Dependencies are inferred from the claim text.