Non-volatile memory and operating method thereof
AssigneeeMemory Technology Inc.
InventorsHsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
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Abstract
A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.
Claims17
A non-volatile memory, at least comprising:
- a substrate;
- a well, disposed in the substrate;
- a first doped region, a second doped region, and a third doped region, disposed in the well respectively, wherein the second doped region is disposed between the first doped region and the third doped region;
- a first gate structure, disposed on the substrate between the first doped region and the second doped region;
- and
- a second gate structure, disposed on the substrate between the second doped region and the third doped region, the second gate structure comprising a tunneling dielectric layer, a charge trapping material, and a gate from the bottom up, wherein the charge trapping material consists of a material with spatially spread and separated electrical-potential traps, and the charge trapping material disposed on the well directly.
A method for operating a p-channel non-volatile memory comprising a select transistor and a memory transistor serially connected on a substrate, wherein the source of the select transistor is electrically coupled to a source line, the drain of the select transistor is serially connected to a source of the memory transistor, the memory transistor comprises a tunneling dielectric layer, a charge trapping structure, and a gate from the bottom up, a drain of the memory transistor is electrically coupled to a bit line;
- the operating method comprising:
- during the erase operation, applying a first voltage onto a gate of the memory transistor, applying a second voltage onto the drain of the memory transistor, applying a third voltage onto the substrate, and floating the source of the select transistor or applying a fourth voltage onto the gate of the select transistor to turn off the select transistor, so as to attract the electrons to enter the gate from the charge trapping structure, or to inject the holes into the charge trapping structure from the gate for erasing the memory transistor, wherein the first voltage is greater than the second voltage, and the first voltage is greater than the third voltage.
Dependencies are inferred from the claim text.