Semiconductor device and method of manufacturing the same
AssigneeElpida Memory, Inc.
InventorKiyonori Oyu
Life of this patent
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Abstract
A method of manufacturing a semiconductor device includes: (A) a wafer process; and (B) a bias application process after the wafer process. The wafer process includes: (a) forming a n-type well in a p-type semiconductor substrate; (b) forming a p-type well in the n-type well; and (c) forming a transistor on the p-type well, the transistor having a n-type source/drain diffusion layer. In the bias application process, a forward bias is applied between the p-type well and the n-type well to move heavy metal ions.
Claims19
A method of manufacturing a semiconductor device comprising:
- forming a n-type well in a p-type semiconductor substrate;
- forming a p-type well in said n-type well;
- forming a transistor on said p-type well, said transistor having a n-type source/drain diffusion layer;
- and
- applying a forward bias between said p-type well and said n-type well to remove heavy metal ions from a p-n junction between said p-type well and said n-type well, formed during at least one of the forming of the n-type well, the forming of the p-type well, and the forming of the transistor.
A method of manufacturing a semiconductor device in a semiconductor wafer comprising:
- forming a n-type well in a p-type semiconductor substrate within said semiconductor wafer;
- forming a p-type well in said n-type well;
- forming a transistor on said p-type well, said transistor having a n-type source/drain diffusion layer;
- inspecting circuit characteristics of the semiconductor device;
- dicing said semiconductor wafer to produce a semiconductor chip and packaging said semiconductor chip;
- and
- inspecting circuit characteristics of said semiconductor chip,
- wherein a forward bias between said p-type well and said n-type well to remove heavy metal ions from a p-n junction between said p-type well and said n-type well, formed during at least one of the forming of the n-type well, the forming of the p-type well, and the forming of the transistor, is applied at, at least one of, a time between said formation of the semiconductor device and inspection of the circuit characteristics of the semiconductor device, a time when dicing said semiconductor wafer, and a time between dicing said semiconductor wafer and inspecting circuit characteristics of said semiconductor chip.
Dependencies are inferred from the claim text.