MOS device and process having low resistance silicide interface using additional source/drain implant

A method of forming a NMOS transistor, comprising the steps of:

• providing a semiconductor substrate;
• forming a gate electrode over a gate insulator;
• forming a source and drain by performing a first n+S/D implant, said source and drain separated by a p-type channel region having said gate electrode and said gate insulator thereon, and
• implanting a second n+S/D implant into a surface portion of said source and said drain, wherein said second n+S/D implant comprises an As dose of 5×1014 to 2.2×1015 cm−2 at an energy of 1.5 to 2.5 KeV;
• annealing said first and second n+S/D implants;
• pre-amorphizing an interface region at a surface portion of said source and said drain;
• depositing a metal comprising interface layer on said interface region;
• performing a silicide anneal at a temperature of <500 C to form a silicide layer and partially activate dopant provided by said first and second n+S/D implants, wherein at said interface region a total chemical dopant concentration of n-type dopant is at least 5×1020 cm3.