Manufacturing method of thin film transistor array substrate and liquid crystal display panel

A manufacturing method of a thin film transistor array substrate, comprising:

• providing a substrate having at least a display region and a sensing region;
• forming a patterned semiconductor layer on the substrate, wherein the patterned semiconductor layer includes a semiconductor block and a first storage electrode in the display region;
• performing ion doping on the semiconductor block and the first storage electrode, wherein a doped source region, a doped drain region, and a channel region between the doped source region and the doped drain region are formed in the semiconductor block;
• forming a gate insulation layer on the substrate to cover the semiconductor block and the first storage electrode;
• forming a first patterned metal layer on the gate insulation layer, wherein the first patterned metal layer includes a gate electrode corresponding to the channel region and a second storage electrodes corresponding to the first storage electrode;
• forming an inter-layer dielectric layer on the gate insulation layer to cover the first patterned metal layer;
• forming a plurality of first via holes in the inter-layer dielectric layer and the gate insulation layer, wherein the first via holes respectively expose the corresponding doped source region, doped drain region, and first storage electrode;
• forming a second patterned metal layer on the inter-layer dielectric layer and filling the second patterned metal layer in the first via holes, wherein the second patterned metal layer comprises at least a connecting metal line and a first sensing electrode in the sensing region and the first storage electrode is electrically connected to the doped drain region through the connecting metal line;
• forming a patterned photo sensitive dielectric layer on the first sensing electrode;
• forming a protection layer on the inter-layer dielectric layer to cover the second patterned metal layer and the patterned photo sensitive dielectric layer;
• forming a plurality of second via holes and an opening in the protection layer, wherein the second via holes respectively expose the corresponding connecting metal line and the opening exposes the patterned photo sensitive dielectric layer;
• and
• forming a patterned transparent conductive layer on the protective layer and filling the patterned transparent conductive layer in the second via holes and the opening, wherein the patterned transparent conductive layer comprises a pixel electrode and a second sensing electrode, the pixel electrode is coupled to the corresponding connecting metal line through the corresponding second via hole, and the second sensing electrode is stacked on the patterned photo sensitive dielectric layer through the opening.