Chip scale package (CSP) assembly apparatus and method
AssigneeShanghai Kaihong Technology Co., Ltd.
InventorsTan Xiaochun, Li Yunfang
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Abstract
In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. Such method has improved efficiency as compared to many existing methods of fabricating CSPs.
Claims18
A method of assembling a chip scale package (CSP), comprising the steps of:
- mounting a semiconductor wafer on adhesive tape, wherein said semiconductor wafer includes a plurality of conductive bumps on a top side, and said adhesive tape adheres to said top side;
- sawing said semiconductor wafer a first time such that a sawing kerf is obtained;
- molding said semiconductor wafer with a molding compound such that said molding compound is in said sawing kerf;
- sawing said semiconductor wafer a second time such that a plurality of CSPs are formed from said semiconductor wafer;
- and
- wherein said molding compound covers a top, a bottom, and sidewall surfaces of each semiconductor die.
A chip scale package (CSP), said CSP produced by a method comprising the steps of:
- mounting a semiconductor wafer on adhesive tape, wherein said semiconductor wafer includes a plurality of conductive bumps on a top side, and said adhesive tape adheres to said top side;
- sawing said semiconductor wafer a first time such that a sawing kerf is obtained;
- molding said semiconductor wafer with a molding compound such that said molding compound is in said sawing kerf;
- sawing said semiconductor wafer a second time such that a plurality of CSPs are formed from said semiconductor wafer;
- wherein said molding compound covers a top, a bottom, and sidewall surfaces of each semiconductor die.
Dependencies are inferred from the claim text.