Single and double-gate pseudo-FET devices for semiconductor materials evaluation
AssigneeInternational Business Machines Corporation
InventorsHarold J. Hovel, Thermon E. McKoy
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AssigneeInternational Business Machines Corporation
InventorsHarold J. Hovel, Thermon E. McKoy
Estimating the term…
Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.
A process for creating offset multiple layers of source and drain metal electrodes in an FET device test structure comprising:
Dependencies are inferred from the claim text.