Locked prefetch scheduling in general cyclic regions
AssigneeSun Microsystems, Inc.
InventorsPartha P. Tirumalai, Spiros Kalogeropulos, Yonghong Song
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Abstract
One embodiment of the present invention provides a system that facilitates locked prefetch scheduling in general cyclic regions of a computer program. The system operates by first receiving a source code for the computer program and compiling the source code into intermediate code. The system then performs a trace detection on the intermediate code. Next, the system inserts prefetch instructions and corresponding locks into the intermediate code. Finally, the system generates executable code from the intermediate code, wherein a lock for a given prefetch instruction prevents subsequent prefetches from being issued until the data value returns for the given prefetch instruction.
Claims15
A method for locked prefetch scheduling in general cyclic regions of a computer program, comprising:
- receiving source code for the computer program;
- compiling the source code into intermediate code;
- performing a trace detection on the intermediate code to identify a cyclic region in the intermediate code;
- inserting prefetch instructions and corresponding locks into the intermediate code, wherein each prefetch instruction is paired with a lock, and wherein each lock is inserted a number of instructions after a corresponding prefetch instruction, wherein the number of instructions is computed based on at least one of a maximum number of outstanding prefetches allowed and a number of accesses in the cyclic region;
- and
- generating executable code from the intermediate code;
- wherein a lock for a given prefetch instruction prevents subsequent prefetches from being issued until the data value returns for the given prefetch instruction;
- and
- wherein the method is implemented by a computer system that comprises a processor and a memory.
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for locked prefetch scheduling in general cyclic regions of a computer program, the method comprising:
- receiving source code for the computer program;
- compiling the source code into intermediate code;
- performing a trace detection on the intermediate code to identify a cyclic region in the intermediate code;
- inserting prefetch instructions and corresponding locks into the intermediate code, wherein each prefetch instruction is paired with a lock, and wherein each lock is inserted a number of instructions after a corresponding prefetch instruction wherein the number of instructions is computed based on at least one of a maximum number of outstanding prefetches allowed and a number of accesses in the cyclic region;
- and
- generating executable code from the intermediate code;
- wherein a lock for a given prefetch instruction prevents subsequent prefetches from being issued until the data value returns for the given prefetch instruction.
A computer system for locked prefetch scheduling in general cyclic regions of a computer program, comprising:
- a processor;
- a memory;
- a receiving mechanism configured to receive source code for the computer program;
- a compiling mechanism configured to compile the source code into intermediate code;
- a trace detection mechanism configured to perform a trace detection on the intermediate code;
- an identifying mechanism configured to identify a cyclic region of the intermediate code;
- an inserting mechanism configured to insert prefetch instructions and corresponding locks into the intermediate code, wherein each prefetch instruction is paired with a lock, and wherein each lock is inserted a number of instructions after a corresponding prefetch instruction, wherein the number of instructions is computed based on at least one of a maximum number of outstanding prefetches allowed and a number of accesses in the cyclic region;
- and
- a generating mechanism configured to generate executable code from the intermediate code;
- wherein a lock for a given prefetch instruction prevents subsequent prefetches from being issued until the data value returns for the given prefetch instruction.
Dependencies are inferred from the claim text.