US 7,681,167 B2Granted

System and apparatus for designing layout of a LSI

AssigneeNEC Corporation

InventorTakashi Goto

Life of this patent

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Abstract

A judgment section determines whether or not a reduction in the power dissipation is possible by relocation of an improvement-target cell. If a reduction in the power dissipation is possible, a calculation section calculates the delay time of a target path including the improvement-target cell to obtain a possible shift distance of the improvement-target cell, within which the timing constraint is satisfied. A layout change section relocates the improvement-target cell within a range in which the power dissipation can be reduced and timing constraint can be satisfied.

Claims31

Dependent claims

A layout design apparatus for designing layout of a semiconductor device, comprising:

an input section for a receiving circuit-connection data including a plurality of cells in the semiconductor device and a plurality of nets connecting said cells, and an arrangement/interconnect data including an arrangement of said cells and an interconnect length of said nets;
a power-dissipation calculation section for calculating a power dissipation of the semiconductor device based on said circuit-connection data, said arrangement/interconnect data, and a power dissipation library data including a power dissipation of a plurality of cells and a plurality of nets for use in the semiconductor device;
an improvement-target-cell extraction section for extracting an improvement-target cell based on said circuit-connection data;
a power-dissipation-reduction-possibility judgment section for judging whether a reduction in the power dissipation is possible by a relocation of said improvement-target cell in a specific shift distance, and assuming said relocation of said improvement-target cell and an associated change in said interconnect length in said arrangement/interconnect data and comparing power dissipations before and after said assumed relocation of said improvement-target cell, which are calculated by said power-dissipation calculation section,
a path extracting section for extracting a signal path including said improvement-target cell based on said circuit-connection data after said power-dissipation-reduction-possibility judgment section judges that the reduction in power dissipation is possible;
a possible-cell-shift-distance calculation section for calculating a possible shift distance of said improvement-target cell in said extracted signal path based on a delay library data of a plurality of cells and a plurality of nets for use in the semiconductor device, said possible shift distance satisfying a delay constraint specified for the semiconductor device;
and
a layout change section for relocating said improvement-target cell in said arrangement/interconnect data within a range of a shift distance in which said specific shift distance and said possible shift distance overlap each other, to update said arrangement/interconnect data.

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A method for designing layout of a semiconductor device in a computer system, comprising the steps of:

receiving, by a computer, a circuit-connection data including a plurality of cells in the semiconductor device and a plurality of nets connecting said cells, and an arrangement/interconnect data including an arrangement of said cells and an interconnect length of said nets;
calculating a power dissipation of the semiconductor device based on said circuit-connection data, said arrangement/interconnect data, and power dissipation library data including a power dissipation of a plurality cells and a plurality of nets for use in the semiconductor device;
extracting an improvement-target cell based on said circuit-connection data;
judging whether a reduction in the power dissipation is possible by a relocation of said improvement-target cell in a specific shift distance, and assuming said relocation of said improvement-target cell and an associated change in said interconnect length in said arrangement/interconnect data and comparing power dissipations before and after said assumed relocation of said improvement-target cell, which are calculated in said power dissipation calculating step;
extracting a signal path including said improvement-target cell based on said circuit-connection data after said judging step judges that the reduction in power dissipation is possible;
calculating a possible shift distance of said improvement-target cell in said extracted signal path based on a delay library data of a plurality of cells and a plurality of nets for use in the semiconductor device, said possible shift distance satisfying a delay constraint specified for the semiconductor device;
and
relocating said improvement-target cell in said arrangement/interconnect data within a range of a shift distance in which said specific shift distance and said possible shift distance overlap each other, to update said arrangement/interconnect data.

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A programmable storage medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform a method of mapping an event, said method comprising:

receiving a circuit-connection data including a plurality of cells in the semiconductor device and a plurality of nets connecting said cells, and an arrangement/interconnect data including an arrangement of said cells and an interconnect length of said nets;
calculating a power dissipation of the semiconductor device based on said circuit-connection data, said arrangement/interconnect data, and a power dissipation library data including a power dissipation of a plurality of cells and a plurality of nets for use in the semiconductor device;
extracting an improvement-target cell based on said circuit-connection data;
judging whether a reduction in power dissipation is possible by a relocation of said improvement-target cell in a specific shift distance, and assuming said relocation of said improvement-target cell and an associated change in said interconnect length in said arrangement/interconnect data and comparing power dissipations before and after said assumed relocation of said improvement-target cell, which are calculated in said power dissipation calculating step,
extracting a signal path including said improvement-target cell based on said circuit-connection data after said judging that the reduction in power dissipation is possible;
calculating a possible shift distance of said improvement-target cell in said extracted signal path based on a delay library data of a plurality of cells and a plurality of nets for use in the semiconductor device, said possible shift distance satisfying a delay constraint specified for the semiconductor device;
and
relocating said improvement-target cell in said arrangement/interconnect data within a range of a shift distance in which said specific shift distance and said possible shift distance overlap each other, to update said arrangement/interconnect data.

5 more elements

Dependencies are inferred from the claim text.

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Abstract

A layout design apparatus for designing layout of a semiconductor device, comprising:

an input section for a receiving circuit-connection data including a plurality of cells in the semiconductor device and a plurality of nets connecting said cells, and an arrangement/interconnect data including an arrangement of said cells and an interconnect length of said nets;
a power-dissipation calculation section for calculating a power dissipation of the semiconductor device based on said circuit-connection data, said arrangement/interconnect data, and a power dissipation library data including a power dissipation of a plurality of cells and a plurality of nets for use in the semiconductor device;
an improvement-target-cell extraction section for extracting an improvement-target cell based on said circuit-connection data;
a power-dissipation-reduction-possibility judgment section for judging whether a reduction in the power dissipation is possible by a relocation of said improvement-target cell in a specific shift distance, and assuming said relocation of said improvement-target cell and an associated change in said interconnect length in said arrangement/interconnect data and comparing power dissipations before and after said assumed relocation of said improvement-target cell, which are calculated by said power-dissipation calculation section,
a path extracting section for extracting a signal path including said improvement-target cell based on said circuit-connection data after said power-dissipation-reduction-possibility judgment section judges that the reduction in power dissipation is possible;
a possible-cell-shift-distance calculation section for calculating a possible shift distance of said improvement-target cell in said extracted signal path based on a delay library data of a plurality of cells and a plurality of nets for use in the semiconductor device, said possible shift distance satisfying a delay constraint specified for the semiconductor device;
and
a layout change section for relocating said improvement-target cell in said arrangement/interconnect data within a range of a shift distance in which said specific shift distance and said possible shift distance overlap each other, to update said arrangement/interconnect data.

5 more elements