Method and apparatus for placing an integrated circuit device within an integrated circuit layout

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for placing an integrated circuit (IC) layout for reducing systematic variations that are expected to occur during manufacturing of the IC layout, wherein the method comprises:

• creating one or more continuous rows of diffusion to reduce the systematic variations that are expected to occur during manufacturing of the IC layout;
• placing an IC device within a continuous row of diffusion in the one or more continuous rows of diffusion;
• and
• in response to determining that the IC device is to be electrically isolated from other IC devices,
• inserting, between the IC device and the other IC devices, a transistor which is formed by overlapping the continuous row of diffusion with a gate structure, and
• biasing the transistor by coupling the gate structure to a bias voltage which is either higher than a power supply voltage or lower than a ground voltage to minimize sub-threshold leakage currents.

An apparatus for placing an integrated circuit (IC) layout for reducing systematic variations that are expected to occur during manufacturing of the IC layout, comprising:

• a placement mechanism configured to:
• create one or more continuous rows of diffusion to reduce the systematic variations that are expected to occur during manufacturing of the IC layout;
• place an IC device within a continuous row of diffusion in the one or more continuous rows of diffusion;
• and
• in response to determining that the IC device is to be electrically isolated from other IC devices,
• insert, between the IC device and the other IC devices, a transistor which is formed by overlapping the continuous row of diffusion with a gate structure, and
• bias the transistor by coupling the gate structure to a bias voltage which is either higher than a power supply voltage or lower than a ground voltage to minimize sub-threshold leakage currents.