Circuit delay analyzer, circuit delay analyzing method, and computer product

An apparatus for performing circuit delay analysis on a semiconductor integrated circuit using an all-element delay distribution and a correlation delay distribution, the all-element delay distribution indicating delay based on performance of all circuit elements in a path, the correlation delay distribution indicating delay based on correlation between circuit elements in the path, the apparatus comprising:

• an extracting unit that, from a data set including the all-element delay distributions and the correlation delay distributions of paths in the semiconductor integrated circuit, extracts a first all-element delay distribution and a first correlation delay distribution of a first path among the paths and a second all-element delay distribution and a second correlation delay distribution of a second path among the paths that is parallel to the first path;
• a first calculating unit that calculates a total delay distribution representing a total delay of an integrated path formed by combining the first path and the second path, based on the first all-element delay distribution, the first correlation delay distribution, the second all-element delay distribution, and the second correlation delay distribution;
• a second calculating unit that calculates a third all-element delay distribution of the integrated path based on the first all-element delay distribution and the second all-element delay distribution;
• and
• a third calculating unit that calculates a third correlation delay distribution of the integrated path based on the total delay distribution and the third all-element delay distribution.

A method of performing circuit delay analysis on a semiconductor integrated circuit using an all-element delay distribution and a correlation delay distribution, the all-element delay distribution indicating delay based on performance of all circuit elements in a path, the correlation delay distribution indicating delay based on correlation between circuit elements in the path, the method comprising:

• extracting, from a data set including the all-element delay distributions and the correlation delay distributions of paths in the semiconductor integrated circuit, a first all-element delay distribution and a first correlation delay distribution of a first path among the paths and a second all-element delay distribution and a second correlation delay distribution of a second path among the paths that is parallel to the first path;
• calculating a total delay distribution representing a total delay of an integrated path formed by combining the first path and the second path, based on the first all-element delay distribution, the first correlation delay distribution, the second all-element delay distribution, and the second correlation delay distribution;
• calculating a third all-element delay distribution of the integrated path based on the first all-element delay distribution and the second all-element delay distribution;
• and
• calculating, using a microprocessor of a computer, a third correlation delay distribution of the integrated path based on the total delay distribution and the third all-element delay distribution.