US 7,681,157 B2Granted

Variable threshold system and method for multi-corner static timing analysis

AssigneeInternational Business Machines Corporation

InventorsNathan C. Buck, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Kerim Kalafala, Peihua Qi, Chandramouli Visweswariah, Xiaoyue Wang

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing.

Claims15

Dependent claims

The computerized method of decreasing processing time in multi-corner static timing analysis, the method comprising:

determining an n number of parameters (Pi) defining a full process space {P1, P2, . . . Pn} wherein the n number of parameters are organized in a parameter order from P1 to Pn, the full process space {P1, P2, . . . Pn} including an n number of process sub-spaces each including parameters Pi→n;
assigning a corresponding slack cutoff (ci) {c1, c2, . . . cn} for each parameter of the n number of parameters, wherein each corresponding slack cutoff ci represents an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space {Pi→n};
performing with a static timing analysis device a multi-corner timing analysis utilizing a plurality of the corresponding slack cutoffs (ci) to output an indication of timing verification for one or more paths of an integrated circuit design, wherein said performing a multi-corner timing analysis includes:
conducting a starting corner timing analysis to determine a starting corner slack for each of one or more predetermined paths of an integrated circuit design;
comparing each starting corner slack to slack cutoff c1 to determining any paths having a starting corner slack that fails the slack cutoff c1;
analyzing one or more remaining paths of the paths that fail the previous slack cutoff comparison by varying the next parameter Pi in the parameter order, starting with P1, to each of its non-starting corner parameter values while holding any other unvaried parameter at its starting corner parameter value and holding any previously varied parameter at a corner parameter value that produced its corresponding worst slack value, said analyzing including:
determining a worst slack value for each of the one or more remaining paths;
comparing each worst slack value corresponding to varying Pi with slack cutoff ci+1;
and
determining any paths that have a worst slack value corresponding to varying Pi that fails the slack cutoff ci+1;
and
repeating said analyzing step for each parameter Pi until no paths fail a slack cutoff comparison and/or said varying of Pn−1 is performed;
and
generating a displayable image of the indication of timing verification.

11 more elements

The computerized method of decreasing processing time in multi-corner static timing analysis, the method comprising:

determining an n number of parameters (Pi) defining a full process space {P1, P2, . . . Pn}, wherein the n number of parameters are organized in a parameter order from P1 to Pn based on decreasing impact on variability of timing, the full process space {P1, P2, . . . Pn} including an n number of process sub-spaces each including parameters Pi→n;
assigning a corresponding slack cutoff (ci) {c1, c2, . . . cn} for each parameter of the n number of parameters, wherein each corresponding slack cutoff ci represents an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space {Pi→n};
conducting a starting corner timing analysis with a static timing analysis device to determine a starting corner slack for each of one or more predetermined paths of an integrated circuit design;
comparing with the static timing analysis device each starting corner slack to slack cutoff c1 to determining any paths having a starting corner slack that fails the slack cutoff c1;
analyzing with the static timing analysis device one or more remaining paths of the paths that fail the previous slack cutoff comparison by varying the next parameter Pi in the parameter order, starting with P1, to each of its non-starting corner parameter values while holding any other unvaried parameter at its starting corner parameter value and holding any previously varied parameter at a corner parameter value that produced its corresponding worst slack value, said analyzing including:
determining a worst slack value for each of the one or more remaining paths;
comparing each worst slack value corresponding to varying Pi with slack cutoff ci+1;
and
determining any paths that have a worst slack value corresponding to varying Pi that fails the slack cutoff ci+1;
repeating said analyzing step for each parameter Pi until no paths fail a slack cutoff comparison and/or said varying of Pn-1 is performed;
and
outputting from the computing device an indication of timing verification for one or more of the plurality of paths based on said analyzing.

9 more elements

The computer readable medium containing computer executable instructions implementing a method of decreasing processing time in multi-corner static timing analysis, the instructions comprising:

a set of instructions for determining an n number of parameters (Pi) defining a full process space {P1, P2, . . . Pn}, wherein the n number of parameters are organized in a parameter order from P1 to Pn, the full process space {P1, P2, . . . Pn} including an n number of process sub-spaces each including parameters Pi→n;
a set of instructions for assigning a corresponding slack cutoff (ci) {c1, c2, . . . cn} for each parameter of the n number of parameters, wherein each corresponding slack cutoff ci represents an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space {Pi→n};
and
a set of instructions for performing a multi-corner timing analysis utilizing a plurality of the corresponding slack cutoffs (ci) to output an indication of timing verification for one or more paths of an integrated circuit design, wherein said set of instructions for performing a multi-corner timing analysis includes:
a set of instructions for conducting a starting corner timing analysis to determine a starting corner slack for each of one or more predetermined paths of an integrated circuit design;
a set of instructions for comparing each starting corner slack to slack cutoff c1 to determining any paths having a starting corner slack that fails the slack cutoff Ci;
a set of instructions for analyzing one or more remaining paths of the paths that fail the previous slack cutoff comparison by varying the next pararneter Pi in the parameter order, starting with P1, to each of its non-starting corner parameter values while holding any other unvaried parameter at its starting corner parameter value and holding any previously varied parameter at a corner parameter value that produced its corresponding worst slack value, said set of instructions for analyzing including:
a set of instructions for determining a worst slack value for each of the one or more remaining paths;
a set of instructions for comparing each worst slack value corresponding to varying P1 with slack cutoff ci+1;
and
a set of instructions for determining any paths that have a worst slack value corresponding to varying Pi that fails the slack cutoff ci+1;
and
a set of instructions for repeating said analyzing step for each parameter Pi until no paths fail a slack cutoff comparison and/or said varying of Pn−1 is performed.

10 more elements

Dependencies are inferred from the claim text.