Method of designing and manufacturing semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsShigeyuki Takagi, Shigeru Kinoshita, Hiroshi Watanabe, Toshitake Yaegashi
Life of this patent
Estimating the term…
Abstract
A semiconductor device designing method includes calculating capacitance. The semiconductor device has a semiconductor substrate, an insulator formed on the semiconductor substrate, and an electrode formed on the insulator. The capacitance is calculated under an approximation assuming a portion of the semiconductor substrate, the insulator and a portion of the electrode to be one of a conductor and a dielectric depending on electric characteristics thereof, respectively.
Claims15
A semiconductor device designing method, the semiconductor device having a plurality of memory cells arranged in X-Y direction on a semiconductor substrate, each of the memory cells having a first gate electrode formed on a first insulator provided on the semiconductor substrate and a second gate electrode formed on a second insulator provided on the first gate electrode, the method comprising:
- calculating capacitance under an approximation assuming a portion of the semiconductor substrate, at least one of the first and the second insulators and a portion of the second gate electrode to be one of a conductor and a dielectric depending on electric characteristics thereof, respectively,
- wherein the calculating capacitance includes calculating a capacitance between one of the memory cells and an adjacent memory cell under an approximation assuming an inversion layer portion formed in the semiconductor substrate under the adjacent memory cell to be a conductor and assuming a depletion layer portion formed in the semiconductor substrate under the adjacent memory cell to be a dielectric,
- a capacitance Cfgx between the first gate electrode of one of the memory cells and an adjacent first gate electrode in X-direction,
- a capacitance Cfgy between the first gate electrode of the one of the memory cells and an adjacent first electrode in Y-direction,
- a capacitance Cfgxy between the first gate electrode of the one of the memory cells and an adjacent first gate electrode in a diagonal direction,
- a capacitance Ctun between the first gate electrode of the one of the memory cells and the semiconductor substrate of the one of the memory cells, and
- a capacitance Cono between the first gate electrode of the one of the memory cells and the second gate electrode of the one of the memory cells.
A semiconductor device manufacturing method, the semiconductor device having a semiconductor substrate, an insulator formed on the semiconductor substrate, and an electrode formed on the insulator, the method comprising:
- adjusting sizes of the insulator and the electrode so that a capacitance calculated using a microprocessor under an approximation assuming a portion of the semiconductor substrate, the insulator and a portion of the electrode to be one of a conductor and a dielectric depending on electric characteristics thereof, respectively, is optimized, wherein the capacitance is calculated by calculating,
- a capacitance between one of the memory cells and an adjacent memory cell under an approximation assuming an inversion layer portion formed in the semiconductor substrate under the adjacent memory cell to be a conductor and assuming a depletion layer portion formed in the semiconductor substrate under the adjacent memory cell to be a dielectric,
- a capacitance Cfgx between the first gate electrode of one of the memory cells and an adjacent first gate electrode in X-direction,
- a capacitance Cfgy between the first gate electrode of the one of the memory cells and an adjacent first electrode in Y-direction,
- a capacitance Cfgxy between the first gate electrode of the one of the memory cells and an adjacent first gate electrode in a diagonal direction,
- a capacitance Ctun between the first gate electrode of the one of the memory cells and the semiconductor substrate of the one of the memory cells, and
- a capacitance Cono between the first gate electrode of the one of the memory cells and the second gate electrode of the one of the memory cells.
Dependencies are inferred from the claim text.