Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test

A processor, comprising:

• a central processing unit having a clock input;
• a register configured to receive a test pattern;
• a mode signal generator coupled to the register, wherein the mode signal generator is configured to provide a mode signal, based on the test pattern;
• and
• a clock generator configured to receive a first clock signal, a second clock signal, and the mode signal, wherein the first and second clock signals are out of phase and have the same clock frequency and the clock generator is configured to provide a generated clock signal to the clock input of the central processing unit, and wherein the generated clock signal has an effective frequency that is based on the first and second clock signals and the mode signal, where the mode signal is configured to select a first clock cycle of the generated clock signal and cause at least one of a selected high-phase and a selected low-phase of the first clock cycle to be shrunk relative to a second clock cycle of the generated clock signal.