Test system employing test controller compressing data, data compressing circuit and test method
AssigneeSamsung Electronics Co., Ltd.
InventorHwan-wook Park
Life of this patent
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Abstract
A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the DUT, compressing the serial data bits by m bits (m≧4) in response to a second clock signal to generate a signature signal, and outputting the signature signal to the tester. The tester compares a computed signature signal to a 1-bit signature signal to determine whether the DUT is operating poorly or not.
Claims9
A test system comprising:
- a tester connected to a device under test (DUT) through a test controller,
- the test controller receiving a first clock signal and m-bit serial data output from the DUT, compressing the m-bit serial data in response to a second clock signal to generate a signature signal, and outputting the signature signal to the tester,
- wherein the test controller comprises:
- a shift register including m first flip-flops connected in series, sequentially receiving bits of the m-bit serial data in response to a first clock signal, and respectively providing outputs from the m first flip-flops to m comparators;
- and
- a data compressing circuit compressing the m-bit serial data into the signature signal and comprising:
- m second flip-flops initially storing m-bit initial seed data and respectively receiving outputs from the m comparators in response to the second clock signal generated at a pulse of the first clock signal at which an mth serial bit of the m-bit serial data is input,
- wherein an output of a last flip-flop of the second flip-flops feedback connected to a first comparator of the m comparators is output as the signature signal,
- the m comparators respectively compare (n+1)th outputs of the first flip-flops to nth outputs of the second flip-flops,
- m is greater than or equal to 4, and n is an integer ranging from 1 to (m−1).
A test system comprising:
- a tester connected to a device under test (DUT) through a test controller,
- the test controller receiving a first clock signal and m-bit serial data from the DUT, compressing the m-bit serial data in response to a second clock signal to generate a signature signal, and providing the signature signal to the tester,
- wherein the test controller comprising:
- a shift register including m first flip-flops connected in series, sequentially receiving bits of the m-bit serial data in response to a first clock signal, and respectively providing outputs of the m first flip-flops to m comparators;
- and
- a data compressing circuit compressing the m-bit serial data into at least two signature signals, wherein the data compressing circuit comprises:
- m second flip-flops initially storing m-bit initial seed data and respectively receiving outputs from the m comparators in response to a second clock signal, wherein an output of a last flip-flop of the second flip-flops feedback connected to a first comparator of the m comparators is output as a second signature signal;
- a switch connected to the output of an (m/2)th flip-flop of the second flip-flops and outputting a first signature signal in response to a third clock signal,
- wherein the m comparators respectively compare (n+1)th outputs of the first flip-flops to nth outputs of the second flip-flops,
- m is an even integer greater than or equal to 8 and n is an integer ranging from 1 to (m−1).
Dependencies are inferred from the claim text.