Semiconductor integrated circuit, BIST circuit, design program of BIST circuit, design device of BIST circuit and test method of memory

A BIST circuit comprising;

• an address generation unit to generate an address for a boundary test, the boundary test being an access test to a boundary cell with at least one of a row or a column address pattern of a memory includes a top address or a bottom address, and the address pattern being the row or the column address pattern of the memory and for at least one of the row address pattern or the column address pattern, the top address and the bottom address are alternated;
• and
• an expected value checking unit to check test data read out from the memory with an expected value.

A method performed by a design program product of a BIST circuit to execute a certain operation, the method comprising:

• selecting a pattern of a BIST circuit, the BIST circuit being able to perform a boundary test to conduct an access test for a boundary cell including at least one of row or column addresses of a memory having a alternative a top address and a bottom address;
• and
• generating a BIST circuit using the pattern.

A method of designing a BIST circuits comprising:

• inputting, via a data input unit, the number and a size of a memory;
• and
• generating, via a BIST circuit generation unit, a BIST circuit using data input from the data input unit and a pattern of a BIST circuit, the BIST circuit being able to perform a boundary test to conduct an access test for a boundary cell including at least one of a row or a column address of a memory having a top address or a bottom address.

A method of testing a memory comprising:

• accessing a boundary cell including at least one of a row address or a column address of a memory having a top address or a bottom address;
• and
• reading out data from the boundary cell to check with an expected value.