Back to results
US 7,681,095 B2Granted
Methods and apparatus for testing integrated circuits
AssigneeInternational Business Machines Corporation
InventorsDerick G. Behrends, Peter T. Freiburger, Ryan C. Kivimagi
Life of this patent
Estimating the term…
Abstract
In some aspects, an apparatus is provided. The apparatus includes a plurality of memory arrays, a latch, and a selection circuit coupled to the plurality of memory arrays and to the latch. The selection circuit may be operative to receive a bit from each of a plurality of memory arrays select one of the plurality of memory arrays, and store the bit from the selected memory array. Numerous other aspects are provided.
Claims9
An apparatus comprising:
- a plurality of memory arrays;
- a latch;
- a selection circuit coupled to the plurality of memory arrays and to the latch, and operative to:
- receive a bit from each of the plurality of memory arrays;
- select one of the plurality of memory arrays;
- and
- store the bit from the selected memory array.
4 more elements
An apparatus comprising:
- a first plurality of memory arrays;
- a first latch;
- a first selection circuit coupled to the first plurality of memory arrays and to the first latch, and operative to:
- (a) receive a bit from each of the first plurality of memory arrays;
- (b) select one of the first plurality of memory arrays;
- and
- (c) store the bit from the selected one of the first plurality of memory arrays;
- a second plurality of memory arrays;
- a second latch;
- a second selection circuit coupled to the second plurality of memory arrays and to the second latch, and operative to:
- (d) receive a bit from each of the second plurality of memory arrays;
- (e) select one of the second plurality of memory arrays;
- and
- (f) store the bit from the selected one of the second plurality of memory arrays.
11 more elements
Dependencies are inferred from the claim text.