Debugging a processor through a reset event

A data processing system comprising:

• a processor for executing instructions;
• an internal debug unit coupled to the processor, the internal debug unit comprising:
• a debug control register having a plurality of control bits for storing debug configuration information for a plurality of resources that are shared between a debug operating mode and a normal operating mode;
• and
• a reset control unit coupled to the debug control register for resetting the plurality of control bits of debug control register to an initial state in response to a reset event;
• and
• external debug circuitry coupled to the internal debug unit, the external debug circuitry for controlling a debug operating mode of the processor in response to a debug mode bit of the debug control register being asserted, wherein when the debug mode bit is asserted, the reset control unit is blocked from resetting a predetermined portion of the plurality of control bits in response to a reset event.

A method for operating a data processing system, the method comprising:

• initializing a processor of the data processing system to operate in a normal operating mode, wherein the processor is for executing instructions;
• determining to debug the processor through a reset operation in response to a reset event;
• asserting a debug control signal to cause the processor to enter a debug operating mode;
• initializing a plurality of shared processor resources with debug configuration information, wherein the plurality of shared processor resources are shared between the normal operating mode and the debug operating mode;
• executing instructions with the processor while in the debug operating mode;
• re-initializing the processor in response to a reset event;
• and
• preventing the reset event from re-initialing a predetermined portion of the debug configuration information in response to asserting the debug control signal by writing a first predetermined control value to at least one reset blocking control bit of a debug control register, preventing a first reset event from re-initializing the predetermined portion of the debug configuration information, re-writing the at least one reset blocking control bit with a second predetermined control value in response to the first reset event, and re-initializing the predetermined portion of the debug configuration information in response to a second reset event.