Clock data recovery circuit with circuit loop disablement

A clock data recovery circuit, comprising:

• a detector circuit configured to receive data and clock signals and provide a first signal that indicates leading differences and lagging differences between transitions in the clock signals and transitions in the data;
• an integrator circuit configured to receive the first signal and accumulate the leading differences and the lagging differences to provide a successive approximation signal;
• and
• a phase shift circuit configured to receive the successive approximation signal and to shift the clock signals in response to the successive approximation signal, wherein the detector circuit, the integrator circuit, and the phase shift circuit are configured to form a circuit loop and the phase shift circuit is configured to disable the circuit loop to shift the clock signals and enable the circuit loop to receive another successive approximation signal.

A memory buffer circuit, comprising:

• a clock data recovery circuit configured to receive data and recover a clock signal from the data, the clock data recovery circuit comprising:
• a detector circuit configured to receive the data and the clock signal and to provide a first signal at a first rate, wherein the first signal indicates differences between transitions in the data and transitions in the clock signals;
• a high bandwidth integrator circuit configured to receive the first signal at the first rate to accumulate the differences between transitions in the data and transitions in the clock signals and provide a first shift signal;
• a control circuit configured to receive the first shift signal and reset the high bandwidth integrator circuit and to shift the phase of the clock signal in response to the first shift signal, wherein the phase of the clock is shifted in smaller increments for each successive first shift signal for a selected number of first shift signals.

A clock data recovery circuit comprising:

• means for receiving data;
• means for detecting differences between transitions in the data and transitions in a clock signal;
• means for accumulating the differences to obtain a first shift signal;
• means for disabling accumulation of the differences based on the first shift signal;
• and
• means for phase shifting the clock signal in response to the first shift signal while the accumulation of the differences is disabled.

A method for clock data recovery, comprising:

• providing a clock signal;
• receiving data;
• indicating differences between transitions in the data and transitions in the clock signal;
• accumulating the differences in a first circuit;
• indicating accumulated differences from the first circuit;
• disabling acquisition of another indication of accumulated differences from the first circuit based on the indicated accumulated differences from the first circuit;
• and
• shifting the clock signal based on the indicated accumulated differences from the first circuit while acquisition of another indication of the accumulated differences from the first circuit is disabled.

A method for clock data recovery, comprising:

• providing clock signals;
• receiving data;
• indicating leading and lagging differences between transitions in the data and transitions in the clock signals;
• accumulating the leading and lagging differences;
• acquiring a first indication of accumulated differences;
• disabling acquisition of a second indication of accumulated differences based on the first indication of accumulated differences;
• shifting the clock signals based on the first indication of accumulated differences while acquisition of the second indication of the accumulated differences is disabled;
• enabling acquisition of the second indication of accumulated differences;
• shifting the clock signals based on the second indication of accumulated differences while acquisition of a third indication of the accumulated differences is disabled.

A method of clock data recovery in a memory buffer circuit, comprising:

• providing a clock signal to a detector circuit;
• receiving data at the detector circuit;
• indicating leading and lagging differences between transitions in the data and transitions in the clock signal;
• accumulating the leading and lagging differences at a high bandwidth integrator at a first rate;
• indicating accumulated differences from the high bandwidth integrator;
• receiving the indicated accumulated differences from the high bandwidth integrator at a control circuit;
• resetting the high bandwidth integrator circuit;
• shifting the clock signal while the high bandwidth integrator is reset in response to the indicated accumulated differences from the high bandwidth integrator;
• and
• shifting the clock signal in decreasing increments in response to successive indicated accumulated differences from the high bandwidth integrator.