Synchronous type semiconductor device for high speed data processing

A synchronous type semiconductor device comprising:

• a clock generation circuit that generates first and second internal clock signals having a predetermined phase difference from first and second frequency-divided clock signals having different phases, respectively, the first and second frequency-divided clock signals being obtained by frequency dividing an input clock signal by a frequency divider;
• a first circuit that samples an input chip select signal in synchronization with the input clock signal when the second frequency-divided clock signal is active;
• a second circuit that samples the input chip select signal in synchronization with the input clock signal when the first frequency-divided clock signal is active;
• a third circuit that samples an output signal of said first circuit in synchronization with the first internal clock signal;
• a fourth circuit that samples an output signal of said second circuit in synchronization with the second internal clock signal;
• and
• first and second input buffers that receive a result of a logic operation between the output signal of said first circuit and an output signal of said third circuit and a result of a logic operation between the output signal of said second circuit and an output signal of said fourth circuit as first and second input enable signals, respectively, and sample a common input signal in synchronization with the first and second internal clock signals, respectively, based on enabling instructed by the first and second input enable signals.

A synchronous type semiconductor device comprising:

• a clock generation circuit that receives an input clock signal and generate first and second internal clock signals having a predetermined phase difference therebetween;
• a first circuit that samples an input chip select signal in synchronization with the input clock signal;
• second and third circuits that receive an output signal of said first circuit in common and sample the output signal in synchronization with the first and second internal clock signals, respectively;
• first and second input buffers that receive a result of a logic operation between the output signal of said first circuit and an output signal of said second circuit and a result of a logic operation between the output signal of said first circuit and an output signal of said third circuit as first and second input enable signals, respectively, and sample a common input signal in synchronization with the first and second internal clock signals, respectively, based on enabling instruction by the first and second input enable signals;
• a third input buffer that receives a clock signal;
• and
• a fourth input buffer that receives a chip select signal;
• wherein said clock generation circuit includes:
• a frequency divider that receives a clock signal output from said first input buffer, frequency divides the clock signal, and outputs frequency-divided clock signals;
• and
• a timing adjusting unit that receives the frequency-divided clock signals output from said frequency divider and generates first and second internal clock signals having a predetermined phase difference;
• wherein said first circuit includes a first input circuit control unit that receives an output signal of said second input buffer and an output signal of said first input buffer, and samples the output signal of said second input buffer in synchronization with the output signal of said first input buffer;
• wherein said second circuit includes a second input circuit control unit that receives an output signal of said first input circuit control unit and the first internal clock signal from said timing adjusting unit, and samples the output signal of said first input circuit control unit in synchronization of the first internal clock signal;
• wherein said third circuit includes a third input circuit control unit that receives the output signal of said first input circuit control unit and the second internal clock signal from said timing adjusting unit, and samples the output signal of said first input circuit control unit in synchronization with the second internal clock signal;
• and
• wherein said semiconductor device further comprises:
• a first logic circuit that receives the output signal of said first input circuit control unit and an output signal of said second input circuit control unit, and outputs a result of a logic operation between the two output signals;
• and
• a second logic circuit that receives the output signal of said first input circuit control unit and an output signal of said third input circuit control unit, and outputs a result of a logic operation between the two output signals.

A synchronous type semiconductor device comprising:

• a first input buffer that receives a clock signal;
• a frequency divider that receives a clock signal output from said first input buffer, frequency divides the clock signal, and outputs first and second frequency-divided clock signals having phases thereof being different to each other;
• a timing adjusting unit that receives the first and second frequency-divided clock signals from said frequency divider and generates first and second internal clock signals having a predetermined phase difference therebetween in association with the first and second frequency-divided clock signals, respectively;
• a second input buffer that receives a chip select signal;
• a first input circuit control unit that receives an output signal of said second input buffer and the output signal of said first input buffer, receives the second frequency-divided clock signal as an input control signal, and samples the output signal of said second input buffer in synchronization with the output signal of said first input buffer when the second frequency-divided clock signal is active;
• a second input circuit control unit that receives the output signal of said second input buffer and the output signal of said first input buffer, receives the first frequency-divided clock signal as an input control signal, and samples the output signal of said second buffer in synchronization with the output signal of said first input buffer when the first frequency-divided clock signal is active;
• a third input circuit control unit that receives an output signal of said first input circuit control unit and the first internal clock signal from said timing adjusting unit, and samples the output signal of said first input circuit control unit in synchronization with the first internal clock signal;
• a fourth input circuit control unit that receives an output signal of said second input circuit control unit and the second internal clock signal from said timing adjusting unit, and samples the output signal of said second input circuit control unit in synchronization with the second internal clock signal;
• a first logic circuit that receives the output signal of said first input circuit control unit and an output signal of said third input circuit control unit, and outputs a result of a logic operation between the two output signals;
• and
• a second logic circuit that receives the output signal of said second input circuit control unit and an output signal of said fourth input circuit control unit, and outputs a result of a logic operation between the two output signals.