Power management of non-volatile memory systems
AssigneeLexar Media, Inc.
InventorRobert Edwin Payne
Life of this patent
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Abstract
Methods and apparatus for placing a non-volatile memory systems in one of a number of power-down modes in response to events being monitored are useful in reducing power consumption of the non-volatile memory system. The power-down modes provide for successively less functionality, thus providing for successively less power consumption. A non-volatile memory system thus can respond to the events to place the system in a mode that permits the desired operation or a desired response time for subsequent operations while seeking to minimize power consumption.
Claims29
A controller for a non-volatile memory system, comprising:
- a system bus;
- a power management system in communication with the system bus and comprising a clock oscillator adapted to selectively output a fundamental clock signal, a phase-locked loop adapted to selectively output a second clock signal in response to the fundamental clock signal, and a system clock control adapted to selectively distribute a system clock signal in response to the second clock signal;
- a microprocessor in communication with the system bus;
- a first interface in communication with the system bus and adapted for communication with a non-volatile memory device;
- and
- a second interface in communication with the system bus and adapted for communication with a host system;
- wherein the power management system is adapted to monitor events from sources including at least the first interface and the second interface;
- wherein the power management system is further adapted to select one of a plurality of successive power-down modes in response to the events;
- wherein, in a first power-down mode, the controller is adapted to provide for normal operation;
- wherein, in a second power-down mode, the microprocessor is disabled;
- wherein, in a third power-down mode, the system clock control is further disabled;
- wherein the phase-locked loop is configured to receive the fundamental clock signal from the clock oscillator and to generate the second clock signal by directly multiplying the fundamental clock signal by a multiplication factor that is received at an input of the phase-locked loop;
- and
- wherein the power management system is further adapted to alter the multiplication factor in response to one or more of the events.
A method of operating a non-volatile memory system, comprising:
- monitoring events from at least one source;
- placing the non-volatile memory system in a first power-down mode in response to one or more first events, wherein the first power-down mode permits normal operation of the non-volatile memory system;
- placing the non-volatile memory system in a second power-down mode in response to one or more second events, wherein placing the non-volatile memory system in the second power-down mode comprises disabling a microprocessor of the non-volatile memory system;
- receiving a fundamental clock signal and a multiplication factor at a phase-locked loop of the non-volatile memory system;
- altering the multiplication factor in response to one or more of the monitored events;
- generating a system clock signal at the phase-locked loop by directly multiplying the fundamental clock signal by the multiplication factor;
- and
- placing the non-volatile memory system in a third power-down mode in response to one or more third events, wherein placing the non-volatile memory system in the third power-down mode comprises disabling distribution of the system clock signal of the non-volatile memory system.
Dependencies are inferred from the claim text.